• Journal of Korean Society of Transportation
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• v.12 no.1
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• pp.137-149
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• 1994

The objective of study is to evaluate the effect of speed control hump on traffic operation and accidents. Three sites were investigated for the change of traffic accidents before and after the hump installation. Vehicle speeds approaching the hump were also analyzed. The study revealed that not only the number of traffic accidents but also the accident severity were significantly reduced by the installation of hump. Further, different types of traffic accidents with lower severity were observed after the hump installation. For the effect of speed reduction by hump, it was found that the speeds observed at 15m upstream of hump were in the range of 36~50 percent of approaching speeds which were not affected by (ie, without) the hump. Economic analysis of hump installation showed the benefit-cost ratio of 4.3 and 11.2 at two sites. Further analysis revealed that the benefit by the accident reduction exceeds the cost by speed reduction and installation capital if AADT is below 43,150 vehicles on two lane highways. It is recommended from the study that humps should be considered on two lane highways of high accident locations for excessive speeds to reduce traffic accidents and severity.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.12
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• pp.2258-2263
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• 2006

In this parer, hump characteristics of short-channel nMOSFETs induced by moistures of the ILD(inter-layer dielectric) layer in the shallow trench isolation (STI) process are investigated and the method for hump suppression is proposed Using nMOSFETs with various types of the gate and a measurement of TDS-APIMS (Thermal Desorption System-Atmospheric Pressure ionization Mass Spectrometry), hump characteristics were systematically analyzed and the systemic analysis based hump model was presented; the ILD layer over poly-Si gate of nMOSFET generates moistures, but they can't diffuse out of the SiN layer due to the upper SiN layer. Consequently, they diffuses into the edge between the gate and STI and induces short-channel hump. In order to eliminate moisture in the ILD layer by out-gassing method, the annealing process prior to the deposition of the SiN layer was carried out. As the result, short-channel humps of the nMOSFETs were successfully suppressed.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.05b
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• pp.291-293
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• 2000

In 64M DRAM, sub-1/4m NMOSFETs with STI(Shallow Trench Isolation), anomalous hump phenomenon of subthreshold region, due to capped p-TEOS/SiN interlayer induced defect, is reported. The hump effect was significantly observed as channel length is reduced, which is completely different from previous reports. Channel Boron dopant redistribution due to the defect should be considered to improve hump characteristics besides consideration of STI comer shape and recess.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.319-319
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• 2012

현재 폭넓게 이용되고 있는 STI (Shallow Trench Isolation) 공정에서 active edge 부분에 발생하는 기생 transistor의 subthreshold hump 특성을 제어하는 연구가 활발히 이루어지고 있다. 일반적으로 STI 공정을 이용하는 MOSFET에서 active edge 부분의 얇게 형성된 gate oxide, sharp한 active edge 형성, STI gap-fill 공정 중에 생기는 channel dopant out-diffusion은 subthreshold hump 특성의 주된 요인이다. 이와 같은 문제점을 해결하기 위해 active edge rounding process와 channel dopant compensation의 implantation을 이용하여 subthresold hump 특성 개선을 연구하였다. 본 연구는 STI 공정에 필요한 wafer와 phosphorus를 함유한 wafer를 한 chamber 안에서 auto-doping하는 방법을 이용하여 subthresold hump 특성을 구현하였다. phosphorus를 함유한 wafer에서 빠져나온 phosphorus가 STI 공정중인 wafer로 침투하여, active edge 부분의 channel dopant인 boron 농도를 상대적으로 낮춰 active edge 부분의 가 감소하고 leakage current를 증가시킨다. transistor의 channel length, gate width이고, wafer#No가 클수록 phosphorous를 함유한 wafer까지의 거리는 가까워진다. wafer #01은 hump 특성이 없고, wafer#20은 에서 심한 subthreshold hump 특성을 보였다. channel length 고정, gate width를 ~으로 가변하여 width에 따른 영향을 실험하였다. active 부분에 대한 SCM image로 확인된 phosphorus에 의한 active edge 부분의 boron 농도 감소와 gate width vs curve에서 확인된 phosphorus에 의한 감소가 narrow width로 갈수록 커짐을 확인하였다.

• Journal of the Korean Society for Precision Engineering
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• v.18 no.5
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• pp.112-119
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• 2001

A variety of input shaper has been proposed to reduce the residual vibration of flexible structures. Multi-hump input shaper is known to be robust for parameter variations. However, existing approach should solve the more complicated nonlinear simultaneous equations to improve the robustness of the input shaper with the additional constraints. In this paper, by proposing a graphical approach which uses convolution of shaper, the multi-hump convolution input shaper could be designed even if the constraints are added for further robustness. With a mass-damper-spring model, the better performance is obtained using the proposed new multi-hump convolution input shaper.

• Transactions on Electrical and Electronic Materials
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• v.13 no.1
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• pp.47-49
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• 2012

In this paper, we investigated the anomalous hump in the bottom gate staggered a-IGZO TFTs. During the positive bias stress, a positive threshold voltage shift was observed in the transfer curve and an anomalous hump occurred as the stress time increased. The hump became more serious in higher gate bias stress while it was not observed under the negative bias stress. The analysis of constant gate bias stress indicated that the anomalous hump was influenced by the migration of positively charged mobile interstitial zinc ion towards the top side of the a-IGZO channel layer.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.11
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• pp.900-904
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• 2011

In this paper, we investigated an anomalous hump phenomenon under the positive bias stress in p-type LTPS TFTs. The devices with inferior electrical performance also show larger hump phenomenon. which can be explained by the sub-channel induced from trapped electrons under thinner gate oxide region. We can confirm that the devices with larger hump have larger interface trap density ($D_{it}$) and grain boundary trap density ($N_{trap}$) extracted by low-high frequency capacitance method and Levinson-Proano method, respectively. From the C-V with I-V transfer characteristics, the trapped electrons causing hump seem to be generated particularly from the S/D and gate overlapped region. Based on these analysis, the major cause of an anomalous hump phenomenon under the positive bias stress in p-type poly-Si TFTs is explained by the GIDL occurring in the S/D and gate overlapped region and the traps existing in the channel edge region where the gate oxide becomes thinner, which can be inferred by the fact that the magnitude of the hump is dependent on the average trap densities.

• KSCE Journal of Civil and Environmental Engineering Research
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• v.36 no.6
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• pp.1075-1082
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• 2016

In order to calculate the optimum installation interval between a speed hump and hump type crosswalk that are installed continuously in succession, this study examined the speed of a vehicle that passes different intervals between speed humps and hump type crosswalks from the approach section of a roundabout having a maximum speed limit of 30km/h; analyzed the effects of speed humps and hump type crosswalks installed continuously in succession on vehicle driving speed; and simulated the optimum installation height of hump type crosswalk. As a result, the following conclusion was drawn. First, it was found that the optimum interval between a speed hump and hump type crosswalk, which are the representative traffic calming techniques for reducing vehicle speed, to control vehicle speed under 30km/h is 30m. Second, as a result of comparing the deceleration of a vehicle that pass hump type crosswalks, it was found that if the installation interval is 65 m and above, a speed hump and hump type crosswalk had no effect. Therefore, it is desirable that the maximum installation interval between a speed hump and hump type crosswalk for controlling vehicle speed within a fixed road section should not exceed 65m. Third, the analysis showed that the optimum installation height of hump type crosswalk is 6-8cm in case vehicle speed at the approach section is 20km/h or lower, 8-10cm in case of 30km/h, and 10cm in case of 30km/h or higher, respectively. Fourth, even at a road section on which a speed hump and hump type crosswalk are installed, speed reduction effects may sometimes be insignificant due to a driver's studying effect, traffic conditions and so on. Thus, it is judged that speed reduction effects will be greater if several traffic calming techniques such as speed hump, chicane, and choker are applied at the same time. Therefore, in case of applying traffic calming techniques for the purpose of reducing vehicle speed in order to promote pedestrian safety, the composite application of several techniques should be considered.

• Transactions on Electrical and Electronic Materials
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• v.3 no.3
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• pp.18-20
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• 2002

In sub-l/4 ${\mu}{\textrm}{m}$ NMOSFET with STI (Shallow Trench Isolation), the anomalous hump phenomenon of subthreshold region, due to capped p-TEOS/SiN induced defect, is reported. The hump effect was significantly observed as channel length is reduced, which is completely different from previous reports. Channel boron dopant redistribution due to the defect should be considered to improve hump characteristics besides considerations of STI comer and recess. 130

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.522-529
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• 2013

In this paper, simple but very effective techniques to suppress subthreshold hump effect for high-voltage (HV) complementary metal-oxide-semiconductor (CMOS) technology are presented. Two methods are proposed to suppress subthreshold hump effect using a simple layout modification approach. First, the uniform gate oxide method is based on the concept of an H-shaped gate layout design. Second, the gate work function control method is accomplished by local ion implantation. For our experiments, $0.18{\mu}m$ 20 V class HV CMOS technology is applied for HV MOSFETs fabrication. From the measurements, both proposed methods are very effective for elimination of the inverse narrow width effect (INWE) as well as the subthreshold hump.