• Title/Summary/Keyword: Human Body Model(HBM)

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Electrostatic discharge simulation of tunneling magnetoresistance devices (터널링 자기저항 소자의 정전기 방전 시뮬레이션)

  • Park, S.Y.;Choi, Y.B.;Jo, S.C.
    • Journal of the Korean Magnetics Society
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    • v.12 no.5
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    • pp.168-173
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    • 2002
  • Electrostatic discharge characteristics were studied by connecting human body model (HBM) with tunneling magnetoresistance (TMR) device in this research. TMR samples were converted into electrical equivalent circuit with HBM and it was simulated utilizing PSPICE. Discharge characteristics were observed by changing the component values of the junction model in this equivalent circuit. The results show that resistance and capacitance of the TMR junction were determinative components that dominate the sensitivity of the electrostatic discharge(ESD). Reducing the resistance oi the junction area and lead line is more profitable to increase the recording density rather than increasing the capacitance to improve the endurance for ESD events. Endurance at DC state was performed by checking breakdown and failure voltages for applied DC voltage. HBM voltage that a TMR device could endure was estimated when the DC failure voltage was regarded as the HBM failure voltage.

HBM ESD Tester for On-wafer Test using Flyback Method (Flyback 방식을 이용한 on-wafer용 HBM ESD 테스터 구현)

  • 박창근;염기수
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.6 no.7
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    • pp.1079-1083
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    • 2002
  • We made ESD tester to measure ESD threshold voltage of semiconductor devices. The HBM ESD test is the most popular method to measure the ESD threshold voltage of MMSIC. We use flyback method which is one of the DC-DC converter to get high ESD voltage. With flvback method, we can isolate the 1ow voltage part from the high voltage part of HBM ESD tester. We use an air gap of the relay which is used for switch to satisfy the rise time of ESD standard(MIL-STD). As a result, with the flyback method and the air gap of relay, we can make ESD tester whose parasitic components are minimized.

HBM ESD Tester for On-wafer Test using Flyback Method (Flyback방식을 이용한 on-wafer용 HBM ESD 테스터 구현)

  • 박창근;염기수
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2002.11a
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    • pp.469-472
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    • 2002
  • We made ESD tester to measure ESD threshold voltage of semiconductor devices. The HBM ESD test is the most popular method to measure the ESD threshold voltage of MMIC. We use flyback method which is one of the DC-DC converter to get high ESD voltage. With flyback method, we can isolate the low voltage part from the high voltage part of HBM ESD tester. We use an air gap of the relay which is used for switch to satisfy the rise time of ESD standard(MIL-STll-883D). As a result, with the flyback method and the air gap of relay, we can make ESD tester whose parasitic components are minimized.

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Electrostatic Discharge Analysis of n-MOSFET (n-MOSFET 정전기 방전 분석)

  • 차영호;권태하;최혁환
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.11 no.8
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    • pp.587-595
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    • 1998
  • Transient thermal analysis simulations are carried out using a modeling program to understand the human body model HBM ESD. The devices were simulated a one-dimensional device subjected to ESD stress by solving Poison's equation, the continuity equation, and heat flow equation. A ramp rise with peak ESD voltage during rise time is applied to the device under test and then discharged exponentially through the device. LDD and NMOS structures were studied to evaluate ESD performance, snap back voltages, device heating. Junction heating results in the necessity for increased electron concentration in the space charge region to carry the current by the ESD HBM circuit. The doping profile adihacent to junction determines the amount of charge density and magnitude of the electric field, potential drop, and device heating. Shallow slopes of LDD tend to collect the negative charge and higher potential drops and device heating.

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A Study on the Development of Simulating Tool for Evaluation of Electrostatic Discharge (정전기 방전 평가를 위한 간이형 도구 개발에 관한 연구)

  • Choi, Sang-Won
    • Journal of the Korean Society of Safety
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    • v.26 no.3
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    • pp.15-22
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    • 2011
  • Explosion and fire cause about 30 reported industrial major accidents a year by ignition source which discharge of electrostatic generated to flammable gas, vapor, dust and mixtures. It brings economically and humanly very large loss that accident was caused by fire and explosion from electrostatic discharge. Thus, it is very important that electrostatic discharge energy is to be control below not to be igniting flammable mixtures. There are two kinds of analysis model for electrostatic discharge, human body model and machine model. Human body model is available the parameter of human's electrical equivalent that capacitance is 100 pF, resistance is $1.5k{\Omega}$. To simulate and visualize the electrostatic discharge from human body need a very expensive and high voltage simulator. In this paper, we measured the value of capacitance and resistance concerned with test materials and sizing of specimen and the value of charged voltage concerned with test specimen and distance to develop an electrostatic charge/discharge simulating tool for teaching with which concerned industrial employee and students. The result of experiments, we conformed that the minimum ignition energy of methane-oxygen mixtures meets well the equation $W=1/2CV^2$, and found out that the insulating material and sizing of equivalent value having human body mode are the poly ethylene of 200 mm and 300 mm of diameter. Developed electrostatic charge/discharge simulating tool has many merits; simple mechanism, low cost, no need of electric power and so on.

Reliability Analysis of CMOS Circuits on Electorstatic Discharge (CMOS 회로의 ESD에대한 신뢰성 문제 및 보호대책)

  • 홍성모;원태영
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.30A no.12
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    • pp.88-97
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    • 1993
  • Electrostatic Discharge(ESD) is one of the major reliability, issues for today's VLSI production. Since the gate oxide with a thickness of 100~300$\AA$ is vulnerable to several thousand volt of ESD surge, it is necessary to control the ESD events and design an efficient protection circuit. In this paper, physical mechanism of the catastrophic ESD damage is investigated by transient analysis based upon Human Body Model(HBM). Using two-dimensional electrothermal simulator, we study the failure mechanism of the output protection devices by ESD and discuss the design issues for the optimun protection network.

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Bidirectional Transient Voltage Suppression Diodes for the Protection of High Speed Data Line from Electrostatic Discharge Shocks

  • Bouangeune, Daoheung;Choi, Sang-Sig;Choi, Chel-Jong;Cho, Deok-Ho;Shim, Kyu-Hwan
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.14 no.1
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    • pp.1-7
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    • 2014
  • A bidirectional transient voltage suppression (TVS) diode consisting of specially designed $p^--n^{{+}+}-p^-$ multi-junctions was developed using low temperature (LT) epitaxy and fabrication processes. Its electrostatic discharge (ESD) performance was investigated using I-V, C-V, and various ESD tests including the human body model (HBM), machine model (MM) and IEC 61000-4-2 (IEC) analysis. The symmetrical structure with very sharp and uniform bidirectional multi-junctions yields good symmetrical I-V behavior over a wide range of operating temperature of 300 K-450 K and low capacitance as 6.9 pF at 1 MHz. In addition, a very thin and heavily doped $n^{{+}+}$ layer enabled I-V curves steep rise after breakdown without snapback phenomenon, then resulted in small dynamic resistance as $0.2{\Omega}$, and leakage current completely suppressed down to pA. Manufactured bidirectional TVS diodes were capable of withstanding ${\pm}4.0$ kV of MM and ${\pm}14$ kV of IEC, and exceeding ${\pm}8$ kV of HBM, while maintaining reliable I-V characteristics. Such an excellent ESD performance of low capacitance and dynamic resistance is attributed to the abruptness and very unique profiles designed very precisely in $p^--n^{{+}+}-p^-$ multi-junctions.

Charged Cable Model (CCM) ESD Damage to ECU (Charged Cable Model (CCM) 정전기 방전(ESD)에 의한 전자제어장치의 손상)

  • Ha, MyongSoo;Jung, JaeMin
    • Transactions of the Korean Society of Automotive Engineers
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    • v.21 no.2
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    • pp.159-165
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    • 2013
  • ESD damage by Charged Cable Model (CCM) is introduced. Due to its own impedance characteristic unlike Human Body Model (HBM) or Machine Model (MM) electric component can be destroyed even though it is located after typical protection circuit. Possible mechanism of ESD damage to automotive electric control unit (ECU) in vehicle environment by CCM discharge was investigated. Based on investigation, field-returned vehicle whose ECU is expected to be damaged by CCM discharge was tested to reproduce it and similar electric component destruction inside ECU was observed. Suggestions to reduce the possibility of ESD damage by CCM are introduced.

A Study on the Optimization of the Layout for the ESD Protection Circuit in O.18um CMOS Silicide Process

  • Lim Ho Jeong;Park Jae Eun;Kim Tae Hwan;Kwack Kae Dal
    • Proceedings of the IEEK Conference
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    • 2004.08c
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    • pp.455-459
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    • 2004
  • Electrostatic discharge(ESD) is a serious reliability concern. It causes approximately most of all field failures of integrated circuits. Inevitably, future IC technologies will shrink the dimensions of interconnects, gate oxides, and junction depths, causing ICs to be increasingly susceptible to ESD-induced damage [1][2][3]. This thesis shows the optimization of the ESD protection circuit based on the tested results of MM (Machine Model) and HBM (Human Body Model), regardless of existing Reference in fully silicided 0.18 um CMOS process. His thesis found that, by the formation of silicide in a source and drain contact, the dimensions around the contact had a less influence on the ESD robustness and the channel width had a large influence on the ESD robustness [8].

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Structure Optimization of ESD Diodes for Input Protection of CMOS RF ICs

  • Choi, Jin-Young
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.17 no.3
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    • pp.401-410
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    • 2017
  • In this work, we show that the excessive lattice heating problem due to parasitic pnp transistor action in the diode electrostatic discharge (ESD) protection device in the diode input protection circuit, which is favorably used in CMOS RF ICs, can be solved by adopting a symmetrical cathode structure. To explain how the recipe works, we construct an equivalent circuit for input human-body model (HBM) test environment of a CMOS chip equipped with the diode protection circuit, and execute mixed-mode transient simulations utilizing a 2-dimensional device simulator. We attempt an in-depth comparison study by varying device structures to suggest valuable design guidelines in designing the protection diodes connected to the $V_{DD}$ and $V_{SS}$ buses. Even though this work is based on mixed-mode simulations utilizing device and circuit simulators, the analysis given in this work clearly explain the mechanism involved, which cannot be done by measurements.