• JSTS:Journal of Semiconductor Technology and Science
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• 제15권6호
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• pp.585-593
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• 2015

In the nanoscale regime, many multigate devices are explored to reduce their size further and to enhance their performance. In this paper, design of a novel device called, Triple Material Surrounding Gate Tunnel Field effect transistor (TMSGTFET) has been developed and proposed. The advantages of surrounding gate and tunnel FET are combined to form a new structure. The gate material surrounding the device is replaced by three gate materials of different work functions in order to curb the short channel effects. A 2-D analytical modeling of the surface potential, lateral electric field, vertical electric field and drain current of the device is done, and the results are discussed. A step up potential profile is obtained which screens the drain potential, thus reducing the drain control over the channel. This results in appreciable diminishing of short channel effects and hot carrier effects. The proposed model also shows improved ON current. The excellent device characteristics predicted by the model are validated using TCAD simulation, thus ensuring the accuracy of our model.

• 설비공학논문집
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• 제13권10호
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• pp.930-938
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• 2001

In this study, evaporation pressure drop experiments were conducted with two types of plate and shell heat exchangers (P&SHE) using R-22. An experimental refrigerant loop has been established to measure the evaporation pressure drop of R-22 in a vertical P&SHE. The flow channels were formed by adding three plates having a corrugated channel of a chevron angle of $45^{\circ}$. The R-22 flows down in one channel exchanging heat with the hot water flowing up in the other channel. The effect of the refrigerant mass flux, average heat flux, system pressure and vapor quality were explored in detail. During the experiment, the quality change between the inlet and outlet of the refrigerant channel ranges from 0.03 to 0.15. The present data showed that two types of P&SHE have similar trends. The pressure drop increases with the vapor quality for both types of P&SHE. At a higher mass flux, the pressure drop is higher for the entire range of the vapor quality. Also, the increase in the average heat flux increases the pressure drop. Finally, at a higher system pressure, the pressure drop is found to be slightly lower.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제14권11호
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• pp.4426-4442
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• 2020

Since scene segmentation is becoming a hot topic in the field of autonomous driving and medical image analysis, researchers are actively trying new methods to improve segmentation accuracy. At present, the main issues in image semantic segmentation are intra-class inconsistency and inter-class indistinction. From our analysis, the lack of global information as well as macroscopic discrimination on the object are the two main reasons. In this paper, we propose a Densely connected residual Attention network (DA-Res2Net) which consists of a dense residual network and channel attention guidance module to deal with these problems and improve the accuracy of image segmentation. Specifically, in order to make the extracted features equipped with stronger multi-scale characteristics, a densely connected residual network is proposed as a feature extractor. Furthermore, to improve the representativeness of each channel feature, we design a Channel-Attention-Guide module to make the model focusing on the high-level semantic features and low-level location features simultaneously. Experimental results show that the method achieves significant performance on various datasets. Compared to other state-of-the-art methods, the proposed method reaches the mean IOU accuracy of 83.2% on PASCAL VOC 2012 and 79.7% on Cityscapes dataset, respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권4호
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• pp.367-380
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• 2013

In this paper, an analytical threshold voltage model is developed for a short-channel double-material-gate (DMG) strained-silicon (s-Si) on silicon-germanium ($Si_{1-X}Ge_X$) MOSFET structure. The proposed threshold voltage model is based on the so called virtual-cathode potential formulation. The virtual-cathode potential is taken as minimum channel potential along the transverse direction of the channel and is derived from two-dimensional (2D) potential distribution of channel region. The 2D channel potential is formulated by solving the 2D Poisson's equation with suitable boundary conditions in both the strained-Si layer and relaxed $Si_{1-X}Ge_X$ layer. The effects of a number of device parameters like the Ge mole fraction, Si film thickness and gate-length ratio have been considered on threshold voltage. Further, the drain induced barrier lowering (DIBL) has also been analyzed for gate-length ratio and amount of strain variations. The validity of the present 2D analytical model is verified with ATLAS$^{TM}$, a 2D device simulator from Silvaco Inc.

• 한국통신학회논문지
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• 제33권12B호
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• pp.1050-1057
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• 2008

무선 메쉬 네트워크 (Wireless Mesh Network, WMN)는 최근 들어 무선 접속 네트워크에서 높은 네트워크 용량을 지원하기 위해 중요한 이슈로 대두되고 있다. WMN에서 주로 사용하는 네트워크 인터페이스 기술인 IEEE 802.11 표준에서는 IEEE 802.11b/g 또는 IEEE 802.11a와 같은 스펙에 따라 3개 또는 12개의 멀티채널을 지원한다. 하지만, WMN에서 채널 할당 알고리즘을 디자인 할 때 두 가지 중요한 문제, 즉 채널 의존성 문제와 채널 스캐닝 딜레이를 고려해야 한다. 채널 의존성 문제는 인터페이스의 동적인 채널 변경이 노드 연결성을 유지하기 위해 다른 인터페이스의 채널 변경을 일으키는 문제이다. 또한, 채널 스캐닝 밀레이는 인터페이스가 채널을 변경할 때마다 발생하며 성능에 영향을 미친다. 따라서, 본 논문에서는 멀티채널 WMN환경에서 이러한 문제점들을 위해 메쉬 게이트웨이로부터의 거리에 기반한 채널 할당 (Distance-Based Channel Assignment, DB-CA)을 제안한다. DB-CA에서는 서로 다른 채널을 사용하는 노드들이 통신을 하기 위해 채널 스캐닝을 수행하지 않고 오직 채널 스위칭만 수행하며, WMN의 메쉬 게이트웨이에 가까운 노드들이 사용하는 채널에 미칠 수 있는 간섭을 최소화 한다. 실험 결과를 통해 WMN에서 DB-CA가 기존 채널 할당 방식에 비해 향상된 성능을 나타냄을 확인하였다.

• 천문학회보
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• 제40권2호
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• pp.52.1-52.1
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• 2015

FIMS/SPEAR is a dual-channel far-ultraviolet imaging spectrograph on board the Korean microsatellite STSAT-1, which was launched on 2003 September 27. The primary mission goal of FIMS was to conduct a survey of diffuse far UV emissions in our Galaxy. For this purpose, FIMS completed a survey of about 84% of the sky during its operation of a year and a half. The present study aims to analyze this survey data made in the far UV wavelengths to understand the global evolution of our Galaxy. The far UV wavelength band is known to contain important cooling lines of hot gas: hence, the study will show how the hot gas in our Galaxy, produced by stellar winds and supernova explosion, evolves globally to cool down and become mixed with ambient cooler medium. One of the main findings from previous analyses of the FIMS data is that molecular hydrogen exists ubiquitously in our Galaxy. This discovery leads to another important scientific question: how is molecular hydrogen distributed in our Galaxy and how does it affect globally the evolution of our Galaxy as a cold component? Hence, the present study will cover both the hot and cold components of the ISM, which will also provide the opportunity to investigate the interactions between the two.

• 전자공학회논문지A
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• 제32A권6호
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• pp.59-66
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• 1995

The hot electron induced effective channel length modulation (${\Delta}L_{H}$) and HEIP characteristics in PMOSFET's after bidirectional stress are presented. Trapped electron charges in gate oxide and lateral field are calculated from the gate current model, and ${\Delta}L_{H}$(${\Delta}L_{HD},\;{\Delta}L_{HS}$) is calculated using trapped electron charges and lateral field. It has been found that ${\Delta}I_{d}$and ${\Delta}L_{H}$ are more affected by the stress order (Forward-Reverse of Reverse or Reverse-Forward) than the stress direction, and they vary logarithmically with the stress time. In contrast, ${\Delta}V_{t}$ and ${\Delta}V_{pt}$ are more affected by the stress direction thatn the stress order. The correlation between ${\Delta}V_{pt}$ and the stress time can be explanined as the following polynomial functin: ${\Delta}V_{pt}$=AT$^{n}$. It has also been shown that PMOSFET degradation is related with the gate current and the effects of ${\Delta}V_{pt}$ is the most significant.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.142-142
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• 2012

최근 반도체 산업의 발전과 동시에 소자의 집적화에 따른 단채널 효과가 문제되고 있다. 채널 영역에 대한 게이트 영역의 제어능력이 떨어지면서 누설전류의 증가, 문턱전압의 변화가 발생하며, 이를 개선하기 위해 이중게이트 혹은 다중게이트 구조의 트랜지스터가 제안되었다. 하지만 채널길이가 수십나노미터 영역으로 줄어듦에 따라 소스/드레인과 채널간의 접합형성이 어렵고, 고온에서 열처리 과정을 거칠 경우 채널의 유효길이를 제어하기 힘들어진다. 최근에 제안된 Junctionless 트랜지스터의 경우, 소스/드레인과 채널간의 접합이 없기 때문에 접합형성 시 발생하는 공정상의 문제뿐만 아니라 누설전류영역을 개선하며, 기존의 CMOS 공정과 호환되는 이점이 있다. 한편, 집적화되는 반도체 기술에 따라, 동작 시 발생하는 스트레스가 소자의 신뢰성에 중요한 요인으로 작용하게 되며, 현재 Junctionless 트랜지스터의 신뢰성 특성에 관한 연구가 부족한 상황이다. 따라서, 본 연구에서는 Junctionless 트랜지스터의 NBTI 특성과 hot carrier effect에 의한 신뢰성 특성을 분석하였다. Junctionless 트랜지스터의 경우, 축적모드로 동작하기 때문에 스트레스에 의해 유기되는 캐리어의 에너지가 낮다. 그 결과, 반전모드로 동작하는 Junction type의 트랜지스터에 비해 스트레스에 의한 subthreshold swing 기울기의 열화와 문턱전압의 이동이 감소하였다. 또한 소스/드레인과 채널간의 접합이 없기 때문에 hot carrier effect에 의한 게이트 절연막 및 계면에서의 열화가 개선되었다.

• 대한전자공학회논문지
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• 제27권9호
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• pp.1409-1418
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• 1990

Characteristics of NMOS transistors with phosphorus source/drain junctions formed by two-step rapid thermal diffusion (RTD) process using a solid diffusion source have been investigated. Phosphorus profiles after RTD were measured by SIMS analysis. In the case of 1100\ulcorner, 10sec RTD of, P, the specific contact resistance of n+ Si-Al was 2.4x10**-7 \ulcorner-cm\ulcorner which is 1/5 of the As junction The comparison fo P junction devices formed by RTD and conventional As junction devices shows that both short channel effect and hot carrier effect of P junction devices are smaller than those of As junction devices when the devices have same junction depths. P junction device had maximum of 0.4 times lower Isub/Id than As junction device. Characteristics of P junction formed by several different RTD conditions have been compared and 1000\ulcorner RTD sample had the smaller hot carrier generation. Also, it has been shown that the hot carrier generation can be futher reduced by forming the P junctions by 3-step RTD which has RTO-driven-in process additionally.

• 한국전기전자재료학회논문지
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• 제27권12호
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• pp.792-796
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• 2014

In this paper, we investigated the hot carrier reliability of two kinds of device with low threshold voltage (LVT) and regular threshold voltage (RVT) in 65 nm CMOS technology. Contrary to the previous report that devices beyond $0.18{\mu}m$ CMOS technology is dominated by channel hot carrier(CHC) stress rather than drain avalanche hot carrier(DAHC) stress, both of LVT and RVT devices showed that their degradation is dominated by DAHC stress. It is also shown that in case of LVT devices, contribution of interface trap generation to the device degradation is greater under DAHC stress than CHC stress, while there is little difference for RVT devices.