• Title/Summary/Keyword: HomePNA

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Design and Implementation of HomePNA 2.0 MAC Controller Circuit (HomePNA 2.0 MAC Controller 회로의 설계 및 구현)

  • Kim, Jong-Won;Kim, Dae-Young
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.31 no.1A
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    • pp.1-10
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    • 2006
  • The Home Phoneline Networking Alliance(HomePNA) 2.0 technology can establish a home network using existing in-home phone lines, which provides a channel rate of 4-32 Mbps. HomePNA 2.0 Medium Access Control(MAC) protocol adopts an IEEE 802.3 Carrier Sense Multiple Access with Collision Detection(CSMA/CD) access method, Quality of Service(QoS) algorithm, and Distributed Fair Priority Queuing(DFPQ) collision resolution algorithm. In this paper, we describe some performance analysis results of HomePNA 2.0 MAC protocol and the requirements of HomePNA 2.0 MAC controller. Then, we propose the architecture of HomePNA 2.0 MAC controller circuit, show the simulation result of each block included in HomePNA 2.0 MAC controller, and present the HomePNA 2.0 transceiver chip that we have implemented.

Performance Analysis of HomePNA 2.0 MAC Protocol (HomePNA 2.0 MAC 프로토콜의 성능 분석)

  • Kim, Jong-Won;Kim, Dae-Young
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.30 no.10A
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    • pp.877-885
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    • 2005
  • The Home Phoneline Networking Alliance (HomePNA) 2.0 technology can establish a home network using existing in-home phone lines, which provides a channel rate of 4-32 Mbps. HomePNA 2.0 Medium Access Control(MAC) protocol adopts an IEEE 802.3 Carrier Sense Multiple Access with Collision Detection (CSMA/CD) access method, Quality of Service(QoS) algorithm, and Distributed Fair Priority Queuing(DFPQ) collision resolution algorithm. In this paper, we propose some mathematical models about the important elements of HomePNA 2.0 MAC protocol performance, which are Saturation Throughput, Packet Delay and Packet Jitter. Then, we present an overall performance analysis of HomePNA 2.0 MAC protocol along with simulations.

A design of HomePNA2.0 PHY. (10Mbps급 HomePNA2.0 PHY. 회로 설계)

  • 박성희;구기종;김종원
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.27 no.12C
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    • pp.1282-1287
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    • 2002
  • In this Paper, we present the design of 10Mbps HomePNA(Home Phoneline Networking Alliance) PHY which is Home Network Technology using phone-line. It is connected with external interface through MII(Media Independent Interface) and AFE(Analog Front End) Interface. 10Mbps HomePNA PHY is composed with Management Block IEEE 802.3 CSMA/CD MAC(Media Access Control) Block Modulator block and Demodulator block. For their verification, we designed a prototype FPGA PCB board using XPC860T made in Motorola. We verified HomePNA frame data transmission using a driver program based Linux kernel. we verified rate negotiation by HomepNA 2.0 Link Layer Protocol.

Design and Simulation of HomePNA 2.0 MAC Controller Circuit

  • Kim, Jong-Won;Kim, Dae-Young
    • Proceedings of the Korea Society of Information Technology Applications Conference
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    • 2005.11a
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    • pp.179-182
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    • 2005
  • The Home Phoneline Networking Alliance (HomePNA) 2.0 technology can establish a home network using existing in-home phone lines, which provides a channel rate of 4 - 32 Mbps. HomePNA 2.0 Medium Access Control (MAC) protocol adopts an IEEE 802.3 Carrier Sense Multiple Access with Collision Detection (CSMA/CD) access method, a Quality of Service (QoS) algorithm, and a Distributed Fair Priority Queuing (DFPQ) collision resolution algorithm. In this paper, we analyze the HomePNA 2.0 MAC protocol and propose the architecture of HomePNA 2.0 MAC controller circuit. Then, we present the simulation result of each block included in the HomePNA 2.0 MAC controller.

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Performance Evaluation of the HomePNA 3.0 Asynchronous MAC Mode with Collision Management Protocol (HomePNA 3.0 비동기 MAC 모드의 Collision Management Protocol 성능 분석)

  • 김희천;정민영;이태진
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.29 no.7A
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    • pp.727-734
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    • 2004
  • Collision Management Protocol (CMP) efficiently resolves collisions when data frames are transmitted in networks consisting of HomPNA 3.0 asynchronous MAC mode device with random access. Unlike Distributed Fair Priority Queueing (DFPQ) algorithm in HomePNA 2.0 or Binary Exponential Backoff (BEB) algorithm in IEEE 802.11, order of retransmission is decided according to Collision Signaling Sequence (CSS) values allocated to each device. Thus, CMP can minimize the number of mean collisions because order of retransmission is decided in a deterministic way. In this paper. we evaluate the saturation performance of CMP in HomePNA 3.0 using an analytic method.

Design of Receiver Architecture for HomePNA 2.0 Modem (HomePNA 2.0 모뎀 수신부 설계)

  • Choi, Sung-Woo;Kim, Jong-Won
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.29 no.9A
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    • pp.991-997
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    • 2004
  • In this paper, we propose the architecture of modem receiver to fabricate HomePNA 2.0 chip. HomePNA suffers from inferior channel because of bridge tap, the effect of amateur HAM band and so on. To transfer data over such channel, HomePNA 2.0 uses training sequence to equalize channel and uses FD-QAM optionally as modulation method. So modem receiver demodulate QAM based signal and needs optimum architecture that fully uses these transmission feature. As a result of research, we define 2 mode function of modem receiver depending on TX/RX state. In this paper, particularly, we show the algorithm of equalizer, carrier phase recovery and frame synchromzationblock and propose architecture that improve the performance of channel equalization and is stable in operation. In the end, we estimate the performance of proposed HomePNA2.0 modem receiver over HomePNA TEST LOOP using SPW program.

High Speed Implementation of HomePNA 2.0 Frame Processor (HomePNA 2.0 프레임 프로세서의 고속 구현 기법)

  • 강민수;이원철;신요안
    • Proceedings of the IEEK Conference
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    • 2003.07a
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    • pp.533-536
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    • 2003
  • 본 논문에서는 전화선을 이용한 고속 홈네트워크인 HomePNA 2.0 시스템에서 HomePNA 2.0 (H2) 프레임을 만들기 위한 프레임 프로세싱 중, 다항식 나누기 연산을 통한 CRC (Cyclic Redundancy Check) 16비트 생성, HCS (Header Check Sequence) 8비트 생성 및 혼화(Scrambling) 처리에 있어서 입력 8 비트를 동시에 병렬 처리함으로써 기존의 1 비트 입력을 LFSR (Linear Feedback Shift Register)를 사용한 다항식 나누기 연산을 수행했을 때보다 빠른 속도로 H2 프레임을 구현하고자 하는 고속 처리 기법을 제시하고 이의 성능을 검증하였다.

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Design and Implementation of Web-based Home PNA Device Management System (웹 기반 Home PNA 장치 관리 시스템의 설계 및 구현)

  • An, Byeong-O;An, Seong-Jin;Jeong, Jin-Uk
    • The KIPS Transactions:PartC
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    • v.8C no.6
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    • pp.865-874
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    • 2001
  • In this paper, we have designed and implemented Web based Home Phoneline Neworking Aliance(Home PNA)device management, system which can resolve the unfair bandwidth service form may subscribers and manage subscribes using these devices. To manage Home PNA device with Simple Network Management Protocol(SNMP) management elements are classified into system. Port performance, fault functional area based on Management Information Base(MIB) objects from Multi Dwelling Unit(MDU) devices MIB. System management provides configuration information of each MDU devices, and port management provides the current state of subscribes and performs filtering operation against the unauthorized users. And performance management provides traffic information about trunk and subscriber lines. Finally fault management provides fault logging fo the unexpected events and trap message from devices To verify the operability of the proposed system, we have tested it in real network environment.

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The Circuit Design and Implementation of HomePNAl.0 Transceiver (HomePNAl.0 Transceiver의 회로 설계 및 구현)

  • Koo, Ki-Jong;Ryu, Khwang-Hyun;Hong, In-Seong;Kim, Bo-Gwan
    • Proceedings of the IEEK Conference
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    • 2000.11d
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    • pp.131-134
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    • 2000
  • This paper presents the circuit design and implementation of a HomePNA (Home Phoneline Network Alliance) 1M8 PHY transceiver for specification ver1.1. This paper describes a physical medium interface, an Ethernet MAC controller unit interface, and a management interface of the HomePNA transceiver. The designed HomePNA transceiver can support any specifications having more than 32Mbits/sec(maximum in HomePNA ver2.0) transmission rate by changing physical medium interface, because Ethernet MAC controller unit interface has been designed by using MII.

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A Novel collision resolution algorithm in HomePNA 2.0 (HomePNA 2.0에서의 새로운 충돌해결 알고리즘)

  • Yoon Won Jin;Kim Hee Chon;Chung Min Young
    • Proceedings of the Korea Information Processing Society Conference
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    • 2004.11a
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    • pp.579-582
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    • 2004
  • HomePNA(Home Phoneline Networking Alliance)는 가정에서 전화선을 이용하여 2대 이상의 통신기기들을 서로 공유할 수 있도록 하는 네트웍 솔루션으로, HomePNA2.0은 기존의 HomePNAl.0과 호환성을 유지하면서도 10Mbps로 전송 가능한 새로운 규격이다. 1999년에 규격이 발표되었으며, CSMA/CD를 기반으로 한 DFPQ (Distribute Fair Priority Queueing)방식의 충돌해결 방법을 사용하고 있다. 본 논문에서는 기존 DFPQ에 기반을 둔 새로운 알고리즘을 제안하고, 기존 DFPQ와 비교 및 분석한다.

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