• Proceedings of the KIEE Conference
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• 1997.11a
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• pp.518-520
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• 1997

In a space vector PWM inverter, the dc input voltage is utilized to the maximum by an overmodulation technique, which is derived from Fourier series expansion of the reference phase voltage. Data angles such reference angle and holding angle are piecewise-linearized for on-line control. Harmonic components and THD of the output voltage are also analyzed. For disturbance of the dc input voltage, a smooth transition is obtained from a linear range to the six-step mode by the control angle change.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.49 no.5
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• pp.345-351
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• 2000

To improve the current waveform of diode rectifiers, we propose a new operating principle of the voltage diode rectifiers. In the conventional voltage rectifier circuit, relatively large capacitors are used to boost the output voltage, while the proposed circuit uses ones and a small reactor not boost the output voltage but improve the input current waveform. A circuit design method is shown and confirmed simulation. It explained that compared conventional PWM(Pulse-width modulated)inverter with HPWM(Half Pulse-width modulated)inverter. Proposed HPWM inverter eliminated dead-time by lowering switching loss and holding over-shooting. Output voltage and current of this paper were applied for real air-conditioner.

• 전기의세계
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• v.25 no.1
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• pp.104-107
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• 1976

The switching characteristics of Non-crystalline As-Te-Si-Ge thin film device using Ag, In and Al metal for electrode, has been investigated. Threshold voltage and holding current of each sandwich type device varied due the to formation of the potential barrier in between non crystalline solid and electrode interface.

• Journal of IKEEE
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• v.22 no.1
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• pp.80-86
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• 2018

In this paper, we propose a new PNP bipolar insertion type ESD protection circuit with improved electrical characteristics than the existing ESD protection circuits SCR and LVTSCR. The proposed circuit has 8.59V trigger voltage which is about 9V lower than that of the conventional SCR, and the parasitic PNP has one more operation and high robustness characteristics. For the practical design of the proposed ESD protection circuit, the holding voltage was increased by increasing the base length of the parasitic PNP while increasing the variable L. To verify the electrical characteristics of the proposed device, Synopsys T-CAD simulator was used.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.3
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• pp.339-344
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• 2014

This paper presents a novel bipolar junction transistor (BJT) based electrostatic discharge (ESD) protection device. This protection device was designed for 20V power clamps and fabricated by a process with Bipolar-CMOS-DMOS (BCD) $0.18{\mu}m$. The current-voltage characteristics of this protection device was verified by the transmission line pulse (TLP) system and the DC BV characteristic was verified by using a semiconductor parameter analyzer. From the experimental results, the proposed device has a trigger voltage of 29.1V, holding voltage of 22.4V and low on-resistance of approximately $1.6{\Omega}$. In addition, the test of ESD robustness showed that the ESD successfully passed through human body model (HBM) 8kV. In this paper, the operational mechanism of this protection device was investigated by structural analysis of the proposed device. In addition, the proposed device were obtained as stack structures and verified.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.822-824
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• 2007

This paper investigated a gate driver circuit with amorphous silicon for mobile TFT-LCD. In the conventional circuit, the fluctuation of the off-state voltage causes the fluctuation of gate line voltages in the panel and then image quality becomes worse. Newly designed gate driver circuit with dynamic switching inverter and carry out signal reduce the fluctuation of the off-state voltage because dynamic switching inverter is holding the off-state voltage and the delay of carry signal is reduced. The simulation results show that the proposed a-Si:H gate driver has low noise and high stability compared with the conventional one.

• Journal of Power Electronics
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• v.2 no.2
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• pp.77-87
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• 2002

The purpose of this paper is to improve power conversion efficiency of three-phase soft-switching voltage-source inverter with an auxiliary resonant dc link (ARDCL) snubber circuit. Firstly, the operation principle of ARDCL snubber circuit is described. Secondly, this paper proposes an effictive generation method of zero voltage vector for three-phase voltage-source soft-switching inverter in power losses in which power losses in the ARDCL snubber circuit can be reduced. In particular, zero voltage holding interval in the inverter DC busline can be controlled due to the new generation scheme of zero voltage vector. Thirdly, a simulator for power loss analysis for power loss characteristics based on actual system, is developed. the validity of developed. The validity of developed simulator of proved with experimental results. Finally, power efficency of three-phase inverter is estimated according to high carrier frequency by using the simulatior.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.6
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• pp.797-801
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• 2014

This research presented the concept of employing the punch-through diode triggered SCRs (PTTSCR) for low voltage ESD applications such as transient voltage suppression (TVS) devices. In order to demonstrate the better electrical properties, various traditional ESD protection devices, including a silicon controlled rectifier (SCR) and Zener diode, were simulated and analyzed by using the TCAD simulation software. The simulation result demonstrates that the novel PTTSCR device has better performance in responding to ESD properties, including DC dynamic resistance and capacitance, compared to SCR and Zener diode. Furthermore, the proposed PTTSCR device has a low reverse leakage current that is below $10^{-12}$ A, a low capacitance of $0.07fF/mm^2$, and low triggering voltage of 8.5 V at $5.6{\times}10^{-5}$ A. The typical properties couple with the holding voltage of 4.8 V, while the novel PTTSCR device is compatible for protecting the low voltage, high speed ESD protection applications. It proves to be good candidates as ultra-low capacitance TVS devices.

• Proceedings of the KIPE Conference
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• 2018.07a
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• pp.210-212
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• 2018

A new switching mode has been proposed to obtain high power factor and low THD in single stage AC-DC converter. The conventional voltage mode control in critical conduction mode distorts input current shape with poor THD in flyback topology. Once TRIAC dimmer is connected, visible flicker in the LED lamp is easily detected due to a lack of TRAIC holding current near the input voltage zero cross. The newly proposed method can shape the input current by providing a desired reference voltage so that low THD is obtained by ideal sinusoidal input current in case of no dimmer connection and flat input current performs good TRIAC dimmer compatibility in phase-cut dimming condition. To confirm the validity of the proposed method, theoretical analysis and experimental result from 8W dimmable LED lighting system are presented.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.2
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• pp.106-113
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• 2000

This study describes how a properly calibrated simulation method could be used to investigate the latchup immunity characteristics among the various high energy ion implanted CMOS twin well (retro-grade/BILLI/BL) structures. To obtain the accurate quantitative simulation analysis of retrograde well, a global tuning procedure and a set of grid specifications for simulation accuracy and computational efficiency are carried out. The latchup characteristics of BILLI and BL structures are well predicted by applying a calibrated simulation method for retrograde well. By exploring the potential contour, current flow lines, and electron/hole current densities at the holding condition, we have observed that the holding voltage of BL structure is more sensitive to the well design rule (p+to well edge space /n +to well edge space) than to the retrograde well itself.