• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2006.05a
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• pp.69-73
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• 2006

The calculation of depth and duration of a sag is in both methods based on two simple assumptions. One is that due to the short circuit, the voltage drops to a low value immediately magnitude. Another is that when the fault is cleared. the voltage recovers immediately. These assumptions, however, do not hold in the case of a substantial part of the load consisting of electrical motors like in many industrial power systems. During the short circuit, the motors will slow down. Their reacceleration after the fault will increase the load current and thus prolong the voltage sag. This paper will discuss some of the aspects of the influence of induction motors on voltage sags.

• Proceedings of the KIEE Conference
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• 1993.07b
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• pp.1206-1208
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• 1993

This paper is to study and realize a measuring device for complex dielectric constants. The device is consisted in order of interface unit, external RAM, programmable counter, D/A converter, measuring circuit, Sample & Hold circuit, A/D converter and related control circuits. Various excitation waves are digitalized and sent to the 4096 static RAM by personal computer. These data saved in the RAM are converted to analog excitation waves through D/A converter. The frequency of excitation wave is depend on the read-out speed of the RAM according to clock pulses. Such generated waves are applied to dielectrics under test and their responses are sampled and converted to digital data through A/D converter. The computer takes the digital data and calculates finally the complex dielectric constants. The frequencies for Measurement ranges from 0.04 Hz to 10 kHz.

• Proceedings of the KIEE Conference
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• 1993.07b
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• pp.809-811
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• 1993

The load impedance of power lines generally varies with time, areas, and season. Also, the harmonic noises by the power electrical equipments are scattered through the power lines. The received signal level varies with the environment and is not able to detect the PLC(Power Line Carrier) signal. For this reason, it is requried for the signal transmitter to hold the received signal level uniform independently with the variation of the load impedence. In this paper, the power lines are modeled simply and a method keeping the received signal level uniform is suggested through the analysis of the signal transmission characteritics of the PLC coupler using tank circuit.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.4
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• pp.25-35
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• 2002

This work describes an 8b 200MHz time-interleaved subranging analog-to-digital converter (ADC) based on a single-poly digital CMOS process. Two fine ADCs for lower digital bits of the proposed ADC employ a time-sharing double-channel architecture to increase system speed and a new reference voltage switching scheme to reduce settling time of the reference voltages and chip area. The proposed intermeshed resistor string, which generates reference voltages for fine ADCs, improves linearity and settling time of the reference voltages simultaneously. The proposed sample- and-hold amplifier(SHA) is based on a highly linear common-drain amplifier and passive differential circuits to minimize power consumption and chip area with 8b accuracy and employs input dynamic common mode feedback circuits for high dynamic performance at a 200MHz sampling rate. A new encoding circuit in a coarse ADC simplifies the signal processing between the coarse ADC and two successive fine ADCs.

• Journal of the Korean Institute of Telematics and Electronics
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• v.13 no.1
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• pp.11-15
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• 1976

In a MOSFET multivibrator, the gate do not hold into a constant clamp voltage during a conduction period. The analysis of the operation and the 43sign of a MOSFET multivibrator circuit are much more discult than that using a bipolar transistor and a electron tube because of above reason. And therefore, in the designing procedures of the MOSFET monostable multivibrator of this paper, a graphical method is adopted in order to analyze and design easily. The voltage gain curves of the both FETs are drawn using a parameter the voltage Vc across the coupling condenser, and the curves are utilized to investigate the voltages of the drains and the gates and determine the gate bias voltage. The diagram gives also important informations for the design of the multivibrator.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.28-33
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• 2008

This paper presents a continuous-time equalizer adopting a clock loss tracking technique for digital display interface. This technique uses bottom hold circuit to detect the incoming clock loss. The generated loss signal is directly fed to equalizer filters, building adaptive feed-forward loops which contribute the stability of the system. The design was done in $0.18{\mu}m$ CMOS technology. Experimental results summarize that eye-width of minimum 0.7UI is achieved until -33dB channel loss at 1.65Gbps. The average power consumption of the equalizer is a maximum 10mW, a very low value in comparison to those of previous researches, and the effective area is $0.127mm^2$.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.37 no.3
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• pp.1-8
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• 2000

This paper presents a simulation model of the Quadrature detector to demodulate FSK signal, which is widely used in wireless paging system for its simple hardware implementation and economics of It fabrication. Quadrature detecter has nonlinear phase characteristic for changes linear changes of input signal frequency. So until now Quadrature detector system analysis remained a difficult problem and performance analysis has not been carried out adequately On these backgrounds, this paper presents the FSK signal demodulation process using Quadrature detector and optimal performance derived from digital simulation technique. First, PSN(Phase Shift Network) which is composed of analog RLC tank circuit is transformed into its equivalent digital transfer function using First-order-hold theorem. Though the demodulated outputs of the Quadrature detector for 4FSK are 4-level signals, only 2 comparators are used and it is shown that optimal performance can be obtained by choosing operation parameter Q value and threshold level decision which are proposed herein.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.10A
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• pp.776-783
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• 2009

Current-cut circuit is an effective method to obtain low power consumption in wireless communication systems as high speed OFDM. For the operation of current-mode FFT LSI with analog signal processing essentially requires current-mode serial-to-parallel/parallel-to-serial converter with multi input and output structure. However, the Hold-mode operation of current-mode serial-to-parallel/parallel-to-serial converter has unnecessary power consumption. We propose a novel current-mode serial-to-parallel/parallel-to-serial converter with current-cut circuit and full chip simulation results agree with experimental data of low power consumption. The proposed current-mode serial-to-parallel/parallel-to-serial converter promise the wide application of the current-mode analog signal processing in the field of low power wireless communication LSI.

• Proceedings of the KIEE Conference
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• 2000.07d
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• pp.2528-2530
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• 2000

In general, Diode makes a major role in electronic circuit. For example, switching of rectifier, cross current of switching rectifier, energy transfer of electronic element and reverse charge of capacitor, voltage insulation, energy feedback from load to power supply, and such as recovery of storaged energy. Generally, We regard power diode as ideal element, but it has a certain boundary actually, specially, We use diode for detecting circuit peak hold voltage signal. It has cut in voltage. It occurs error of measurement value namely. This error, below in region diode voltage drop (0.7v) measurement value is wholesome signal, Specially, We can not get precision data. Therefore, precision level is low between theoretical and measurement data because of error in actual circuit. Conclusionally, In this paper, We define the error concerning to the power diode characteristics which is used detecting of the minute signal, and recommend the method that minimize measurement error.

• Journal of Power Electronics
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• v.2 no.2
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• pp.77-87
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• 2002

The purpose of this paper is to improve power conversion efficiency of three-phase soft-switching voltage-source inverter with an auxiliary resonant dc link (ARDCL) snubber circuit. Firstly, the operation principle of ARDCL snubber circuit is described. Secondly, this paper proposes an effictive generation method of zero voltage vector for three-phase voltage-source soft-switching inverter in power losses in which power losses in the ARDCL snubber circuit can be reduced. In particular, zero voltage holding interval in the inverter DC busline can be controlled due to the new generation scheme of zero voltage vector. Thirdly, a simulator for power loss analysis for power loss characteristics based on actual system, is developed. the validity of developed. The validity of developed simulator of proved with experimental results. Finally, power efficency of three-phase inverter is estimated according to high carrier frequency by using the simulatior.