• Journal of radiological science and technology
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• v.35 no.4
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• pp.315-319
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• 2012

The aim of this study was to develop a signal process circuit for a position sensitive avalanche photodiode detector. The circuit parts consisted of amplification, differential and peak/hold circuit. This research was the baseline to develop highly compact radiation detector. The signal was amplified by an amplification chip and its shape was changed in a differential circuit to minimize the pulse tailing. The peak/hold circuit detect the peak of the signal from the differential circuit and hold the amplitude of the peak for data acquisition. In order to test the intrinsic function of the circuit, the input signal was transmitted from a commercial pulse generator.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.3
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• pp.53-59
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• 1994

A new fully differential sample-and-hold circuit which can effectively compensate the offset voltage of an operational amplifier and the charge injection of a MOS switch is presented. The proposed circuit shows a true sample-and-hold function without a reset period or an input-track period. The prototype fabricated using a 1.2$\mu$m double-polysilicon CMOS process occupies an area of 550$\mu$m$\times$288$\mu$m and the error of the sampled ouput is 0.056% on average for 3V input at DC.

• Progress in Superconductivity and Cryogenics
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• v.25 no.1
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• pp.16-20
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• 2023

The International Electrotechnical Commission (IEC) 61788-26:2020 provides guidelines for measuring the critical current of Rare-earth barium copper oxide (REBCO) tapes using two methods: linear ramp and step-hold methods. The critical current measurement criterion, 1 or 0.1 μV/cm of electric field from IEC 61788-26 has been normally applied to REBCO coils or magnets. No-insulation (NI) winding technique has many advantages in aspects of electrical and thermal stability and mechanical integrity. However, the leak current from the NI REBCO coil can cause distortion in critical current measurement due to the characteristic resistance which causes the radial current flow paths. In this paper, we simulated the NI REBCO coil by applying both linear ramp and step-hold methods based on a simplified equivalent circuit model. Using the circuit analysis, we analyzed and evaluated both methods. By using the equivalent circuit model, we can evaluate the critical current of the NI REBCO coil, resulting in an estimation error within 0.1%. We also evaluate the accuracy of critical current measurement using both the linear ramp and step-hold methods. The accuracy of the linear ramp method is influenced by the inductive voltage, whereas the accuracy of the step-hold method depends on the duration of the hold-time. An adequate hold time, typically 5 to 10 times the time constant (τ), makes the step-hold method more accurate than the linear ramp method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.4
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• pp.7-14
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• 2012

A image quality is limited by a sample-and-hold circuit of the X-ray CMOS image sensor even though simple mos switch or bootstrapped clock circuit are used to get high quality sampled signal. Because distortion of sampled signal is produced by the charge injection from sample-and-hold circuit even using bootstrapped. This paper presents the 3D micro-inductor design methode in the CMOS process. Using this methode, it is possible to increase the ENOB (effective number of bit) through the use of micro-inductor which is calculated and designed in standard CMOS process in this paper. The ENOB is improved 0.7 bit from 17.64 bit to 18.34 bit without any circuit just by optimized inductor value resulting in verified simulation result. Because of this feature, micro-inductor methode suggested in this paper is able to adapt a mamography that is needed high resolution so that it help to decrease patients dose amount.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.545-548
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• 2004

The paper describes the design of high-speed, high-resolution Sample-and-Hold circuit which shows the conversion rate 80MHz and the power supply of 3.3v with 0.35um CMOS 2-poly 4-metal process for high-speed, high resolution Analog-to-Digital Converter. For improving Dynamic performance of Sample-and-Hold, Two Double bootstrap switch and high performance operational amplifier with gain booster, which are used. and For physical stability of Sample and Hold circuit, reduces excess voltage of gate in bootstrap switch. Simulation results using HSPICE shows the SFDR of 71dB, 75dB in conversion rate of 80MHz result for two inputs(0.5Vpp, 10MHz and 1Vpp, 10MHz) and the power dissipation of 48mW at single 3.3V supply voltage.

• Proceedings of the KIPE Conference
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• 2008.06a
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• pp.382-384
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• 2008

Hold-up time is a special requirement for the front end DC/DC converter in a server power supply. It forces the converter with the variable switching frequency to operate in a wide switching frequency range, which makes the regulation difficult and reduces the power density. In this paper a novel frequency controlled half bridge converter with the hold-up time extension circuit is proposed. During the hold-up time, the auxiliary switches are turned on, thus the resonant inductance is reduced and the voltage conversion ratio is increased. Therefore, the output capacitor of the power factor correction (PFC) circuit can be decreased, and the converter can have high power density. The proposed converter is verified by experimental results from a prototype with 700W, 400V input, and 12V output.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2005.11a
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• pp.191-196
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• 2005

A low-cost, high-performance 40 Gb/s clock recovery module using a phase-locked loop(PLL) for a 40 Gb/s optical receiver has been designed and implemented. It consists of a clock recovery circuit, a RF mixer and frequency discriminator for phase/frequency detection, a DR-VCO, a phase shifter, and a hold circuit. The recovered 40 GHz clock is synchronized with a stable 10 GHz DR-VCO. The clock stability and jitter characteristics of the implemented PLL-based clock recovery module has shown to significantly improve the performance of the conventional open-loop type clock recovery module with DR filter. The measured peak-to-peak RMS jitter is about 230 fs. When input signal is dropped, the 40 GHz clock is generated continuously by hold circuit. The implemented clock recovery module can be used as a low-cost and high-performance receiver module for 40 Gb/s commercial optical network.

• The Transactions of the Korean Institute of Power Electronics
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• v.18 no.5
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• pp.501-506
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• 2013

A hold-up time compensation circuit is proposed to get high efficiency of the front-end phase-shifted full bridge DC/DC converter. The proposed circuit can make the phase-shifted full bridge front-end DC/DC converter built with 0.5 duty ratio so that the conduction loss of the primary side and voltage stress across rectifier in the secondary side are reduced and the higher efficiency can be obtained. Furthermore, the requirement of an output filter significantly can diminish due to the perfect filtered waveform. A 12V/100A prototype has been made and experimental results are given to verify the theoretic analysis and detailed features.

• Journal of Advanced Navigation Technology
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• v.20 no.6
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• pp.612-616
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• 2016

Gamma-ray must be detected and processed immedietely after generation of it in the circumstances where it exists. Software methology may be used to process randomly generated signals, but its memory size and processing time become large. By the way, the hardware circuit to detect randomly generated signals is generalized in industrial site, while those circuits are not able to answer to the cases whose amplitude are very small and also speed high. We researched and developed hardware based peak-hold circuit that is able to detect peaks of gamma-ray signals through direct reading out their values by ADC at the time of maximum reaching for the small amplitude and high speed signals, and proposed and estimated its results in this paper. This peak-hold circuit is adequate to use in the radiation circumstances in which the gamma-rays are heavy because its circuit can catch high speed signals efficiently without software signal processing supports.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.2 s.105
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• pp.171-177
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• 2006

A low-cost, high-performance 40 Gb/s clock recovery module using a phase-locked loop(PLL) for a 40 Gb/s optical receiver with the clock-hold function has been designed and implemented. It consists of a clock extractor circuit, an RF mixer and a frequency discriminator for phase/frequency detection, a VC-DRO, a phase shifter, and a clock-hold circuit. The extracted 40 GHz clock is synchronized with a stable 10 GHz VC-DRO. The clock stability and jitter characteristics of the implemented PLL-based clock recovery module are significantly improved as compared with those of the conventional open-loop type clock recovery module with a DR filter. The measured peak-to-peak RMS jitter is about 230 fs. When an input signal is dropped, the 40 GHz clock is maintained continuously by the hold circuit.