• 전자공학회논문지B
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• 제31B권7호
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• pp.42-48
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• 1994

In this paper, a low power and high speed flash Analog-to-Digital Converter using current-mode concept is proposed. Current-mode approach offers a number of advantages over conventional voltage-mode approach, such as lower power consumption small chip area improved accuracy etc. Rescently this concept was applied to algorithmic A/D Converter. But, its conversion speed is limited to medium speed. Consequently this converter is not applicable to the high speed signal processing system. This ADC is fabricated in 1.2um double metal CMOS standard process. This ADC's conversion time is measured to be 7MHz, and power consumption is 2.0mW, and differential nonlinearity is less than 1.14LSB and total harmonic distortion is -50dB. The active area of analog chip is about 350 x 550u$m^2$. The proposed ADC seems suitable for a single chip design of digital signal processing system required high conversion speed, high resolution small chip area and low power consumption.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권1호
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• pp.829-832
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• 2007

A high-speed and accurate analog buffer is proposed for mobile display using LTPS TFTs. The proposed analog buffer is common source type with sampling and negative feedback mode. Therefore, driving speed of the proposed buffer is faster than previously reported one. In addition, the accuracy is very high because of high negative feedback gain. The simulation results show that maximum mischarging voltage of the proposed buffer is 8mV and previously reported one is 37mV. And Power consumption of the proposed buffer is $43.1{\mu}W$, which is 73% of previously reported one.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.1229-1232
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• 2003

In this paper, The High-speed Low-power Analog-to-Digital Convener Archecture is proposed using the parallel S/H for High-speed operation. This technique can significantly reduce the sampling frequency per S/H channel. The Analog-to-Digital Converter is designed using 0.35${\mu}{\textrm}{m}$ CMOS technology. The simulation result show that the proposed Analog-to-Digital Converter can be operated at 40Ms/s with 8-bit resolution and INL/DNL errors are +0.4LSB~-0.6LSB / +0.9LSB~-1.4LSB , respectively.

• 한국멀티미디어학회논문지
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• 제12권3호
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• pp.329-334
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• 2009

광 디스크를 재생하려면 광 신호를 아날로그 전기신호로 변환하는 광 픽업을 거치고 난 뒤 신호 간 간섭을 없애기 위해 아날로그적으로 등화를 하고, 등화된 아날로그 신호를 AD 변환하여 디지털적으로 동기화된 데이터와 클록을 추출해야 한다. BD와 같은 고용량의 광 디스크를 저속으로 재생하여 동기화된 데이터와 클록을 추출하는데 었어서 추출 데이터 BER을 최소화하는 알고리즘은 다양하게 개발되어 적용되고 있다. 그러나 고용량의 광 디스크를 고속으로 재생 할 때 저속에서 적용된 알고리즘을 동일한 혼성 데이터 PLL과 PRML 하드웨어 구조에 적용하려면 800MHz 이상의 신호 처리가 이루어져야 한다. 일반적으로 사용되는 0.13-${\mu}m$ CMOS 공정에서 기존 방식의 구조를 가지고 800MHz의 이상의 신호처리를 위해서는 고속으로 동작해야하는 아날로그 코어 등이 필요하고 많은 시간과 노력의 레이아웃이 수반되어야 하는 등의 문제점이 제기된다. 본 논문에서는 고용량 광 디스크의 최고 배속인 BD 8x까지 동작 가능한 데이터 및 클록 추출 회로로서 병렬 데이터 PLL 및 PRML 구조를 제안하였다. 제안한 구조를 가지고 실험한 결과 BD 8x 에 해당하는 속도에서 오류 없이 동작함을 확인하였다.

• Journal of Biosystems Engineering
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• 제22권2호
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• pp.117-126
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• 1997

A series of soil bin experiment was carried out on sandy loam to investigate if it is possible to predict implement draft by some analog tool. Chisel configuration resembling a cone penetrometer section was used as an analog tool. The angle of cone was 30 degree. Three types of tillage implement, or oriental janggi, moldboard plow and chisel plow were chosen for this study. Experimental tillage speed was 0.22, 0.33, 0.49 m/s ad tillage depth was 8, 12, 16cm. For the experimental tillage speed range, the increase of tillage speed did not affect the tillage draft for the three types of implement and analog tool, but as the tillage depth increased, tillage draft of the three types of implement and analog tool increased linearly. The linear relationship was found between the tillage draft of analog tool and that of three types of tillage implement for the experimental tillage depth and speed range with high value of $R^2$ Thus it was concluded from the above results that an analog tool can be used to predict the tillage draft of oriental janggi, moldboard plow and chisel plow. But more experiment for various soil types and theoretical verification are needed for more generallization.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2004년도 학술대회 논문집 정보 및 제어부문
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• pp.626-628
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• 2004

This paper describes an 8-bit CMOS folding A/D converter for set-top box. Modular low-power, high-speed CMOS A/D converter for embedded systems aims at design techniques for low-power, high-speed A/D converter processed by the standard CMOS technology. The time-interleaved A/D converter or flash A/D converter are not suitable for the low-power applications. The two-step or multi-step flash A/D converters need a high-speed SHA, which represents a tough task in high-speed analog circuit design. On the other hand, the folding A/D converter is suitable for the low-power, high-speed applications(Embedded system). The simulation results illustrate a conversion rate of 40MSamples/s and a Power dissipation of 80mW(only analog block) at 2.5V supply voltage.

• 대한전자공학회논문지SD
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• 제48권2호
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• pp.55-60
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• 2011

그동안 신경망칩의 설계에는 주로 아날로그 Maximum Selector (MS) 회로를 사용하였다. 그러나 집적도가 높아질수록 아날로그 MS회로는 신호의 해상도(Resolution)을 높이는데 어려움이 있다. 반면 디지털 MS 회로는 높은 해상도를 얻기는 쉬우나 속도가 느린 단점이 있었다. 본 논문에서는 신경망칩의 디지털화에 사용하기 위한 MSIT(Maximum Selector with Internal Trigger-Signal) 라는 고속의 디지털 MS회로를 개발하였다. MSIT는 제어신호 발생기를 내장하여 안정적인 동작을 확보하고, 불필요한 대기시간을 없애도록 이를 최적화 함으로써 높은 속도를 얻을 수 있다. 1.2V-$0.13{\mu}m$ 프로세스의 모델파라메터를 사용하여 32 개의 10 비트 데이터에 대하여 시뮬레이션을 수행한 결과 3.4ns의 응답시간을 얻을 수 있었다. 이는 동급의 해상도를 갖는 아날로그 MS회로 보다 훨씬 빠른 속도로써, MSIT와 같은 디지털 MS 회로가 아날로그 MS회로에 비하여 높은 해상도와 빠른 속도를 구현할 수 있음을 보여준다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권3호
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• pp.300-311
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• 2016

The analog-to-digital-converter-based (ADC-based) backplane receivers that consist of a front-end ADC followed by a digital equalizer are gaining more popularity in recent years, as they support more sophisticated equalization required for high data rates, scale better with fabrication technology, and are more immune to PVT variations. Unfortunately, designing an ADC-based receiver that meets tight power and performance budgets of high-speed backplane link systems is non-trivial as both front-end ADC and digital equalizer can be power consuming and complex when running at high speed. This paper reviews the state of art designs for the front-end ADC and digital equalizers to suggest implementation choices that can achieve high speed while maintaining low power consumption and complexity. Design-space exploration using system-level models of the ADC-based receiver allows through analysis on the impact of design parameters, providing useful information in optimizing the power and performance of the receiver at the early stage of design. The system-level simulation results with newer device parameters reveal that, although the power consumption of the ADC-based receiver may not comparable to the receivers with analog equalizers yet, they will become more attractive as the fabrication technology continues to scale as power consumption of digital equalizer scales well with process.

• ETRI Journal
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• 제29권6호
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• pp.835-837
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• 2007

A multi-bit sigma-delta modulator architecture is described for low-distortion performance and a high-speed operation. The proposed architecture uses both a delayed code and a delayed differential code of analog-to-digital converter in the feedback path, thereby suppressing signal components in the integrators and relaxing the timing requirement of the analog-to-digital converter and the scrambler logic. Implemented by a 0.13 ${\mu}m$ CMOS process, the sigma-delta modulator achieves high linearity. The measured spurious-free dynamic range is 89.1 dB for -6 dBFS input signal.

• 한국정보통신학회논문지
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• 제6권1호
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• pp.25-29
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• 2002

High speed 신호처리는 통신분야, SC circuit, HDTV, ISDN 등에서 관심이 더욱 승가하고 있으며, high speed 신호처리를 위한 많은 방법들이 있다. 본 논문에서는 CMOS 공정에서 고주파 Op-amp의 실현을 의한 설계를 기술하였다. 아날로그 집적회로를 기초로 하는 high speed op-amp의 기능을 제한하는 요소 중 한가지는 유효 주파수 범위이다. 본 논문에서는 $C_{L}$ =2pF에서 단위이득 주파수가 170MHz인 향상된 대역폭적을 가지는 CMOS op-amp 구조를 계발한다. 공정은 1.2$\mu$디자인 룰을 따른다. 본 논문에서 제시한 CMOS op-amp 고주파 SC filter에서 요구하는 큰 커패시터 부하에서의 넓고 안정된 대역폭을 얻기에 매우 적합하다.