• Korean Journal of Optics and Photonics
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• v.9 no.6
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• pp.385-389
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• 1998

In this paper, we propose an optical correlator system using volume holograms for database of matched filters. Optical correlator has high speed and parallel processing characteristics of optics. Matched filters are recorded into a volume hologram that can store data with high density, transfer them with high speed, and select a randomly chosen data element. The multiple reference images of database are prerecorded in a photorefractive crystal in the form of Fourier transform images, simply by passing the image displayed in a spatial light modulator through a Fourier transform lens. The angular multiplexing method for multiple holograms of database can be achieved by rotating the crystal by use of a step motor. Experimental results show that the proposed system can be used for the fingerprint recognition.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.41 no.4
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• pp.454-460
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• 2016

Unlike conventional visible light communications (VLC) adopting photo detectors (PD), optical camera communications (OCC) employs cameras in detecting the transmitted data. Especially, the data rate of OCC can be enhanced by using the principle of rolling-shutter, which is the operating scheme of a CMOS image sensor. In this study, we consider a novel OCC system for high-speed real time video processing to transmit high speed data from LED and to acquire image utilizing rolling-shutter effect of CMOS image sensor. Also, we demonstrate the improved performance of proposed system using a test-bed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.5B
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• pp.465-475
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• 2004

Transport Control Protocol (TCP) has been implemented in software running on CPU in end systems, and the protocol processing has appeared as a new bottleneck due to advanced link technology. TCP processing is a critical issue in Storage Area Network (SAN) such as iSCSL, and the overall performance of the Storage Area Network heavily depends on speed of TCP processing. TCP Engine implemented in hardware reduces the load of CPU in end systems as well as accelerates the protocol processing, and hence high speed data processing is achieved. In this paper, we have proposed a hardware engine for TCP processing. TCP engine consists of three major block, TCP Connection block Rx TCP block and Tx TCP block TCP Connection block is responsible for managing TCP connection states. Rx TCP block is responsible for receive flow which receives packets from network and sends to CPU. Rx TCP performs header and data processing and sends header information to TCP connection block and Tx TCP block It also assembles out-of-ordered data to in-ordered before it transfers data to CPU. Tx TCP block is responsible for transmit flow which transfers data from CPU to network. Tx TCP performs retransmission for reliable data transfer and management of transmit window and sequence number. Various test-cases are used to verify the TCP functions. The TCP Engine is synthesized using 0.18 micron technology and results in 51K gates not including buffers for temporal data storage.

• Journal of Korean Society for Geospatial Information Science
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• v.16 no.3
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• pp.71-78
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• 2008

Nowadays, echosouder has been widely used in sea survey and ship navigation. By utilizing echosounder, we can measure the depth of water reliability. However, the problem is that depth update rate drops remarkably when sea bottom is shallow or steep/rugged. Therefore, we have developed an optimized algorithm to process tranducer's soundwave signals at high-speed and minimize error. Processing algorithm is implemented by the latest DSP processor (TMS320F2812), consequently, high-speed data processing can be achieved. Performance of the proposed algorithm is verified by experiments and compared with existing algorithms. It has shown that our method results in higher precision in water depth measurement than other methods.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.1
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• pp.96-101
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• 2004

In order to measure the retina thickness, there are to need the 3-D retina photographing and the high speed signal processing system. In this paper, we introduced the retina photographing system and the 16-channel high speed image data acquisition system. There are able to measure the retina thickness with sensing image the returned laser signal to APD sensor after there were projected the HeNe laser on retina. We developed the laser projection system to sense a reflected image of the retina using APD sensor, the 16-channel high speed A/D converter and PCI master interface card for image transmission into computer.

• The Transactions of the Korea Information Processing Society
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• v.4 no.2
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• pp.616-627
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• 1997

We porpose a new VLSI architecture for the three step search algorithm for the mition estimation of moving images.In the proposed architecture the regular data input is possible and the data are passed through all computational processes ,minimiuzing the input bandwidth.The performandce is analyzed in detail,and compared with other architectures.The performance is approaching to the ideal computation speed,with less hardware than for the existing architectures.

• Proceedings of the IEEK Conference
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• 2000.11a
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• pp.213-216
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• 2000

In this paper, we propose a new scheme which improves the IP address lookup time. The new scheme is composed of two core technologies, named the prefix alignment and the prefix distance ordering. Now, as the Internet is being used commonly by improving the data transmission capacity, the need for enlarging the bandwidth of the Internet is on the rise. IP address lookup performance problem is an important obstacle in the router executing high speed packet forwarding. This results from the fact that the prefixes routing table is composed of and the traffic being processed in unit time are largely on the increase. The proposed lookup scheme is divided into two parts in technology, the one is the algorithm forming a routing database(routing table), the other is the lookup procedure in the actual packet processing.

• Journal of the Korean Society for Precision Engineering
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• v.16 no.7
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• pp.32-39
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• 1999

Digital signal processor (DSP) is used to obtain the peak value and the time difference of ultrasonic signals, to make digital filter, and to derive mathematical transformation from analog circuit. In this study, C-scan system and control program have been developed to high speed data acquisition. This system consists of signal processing parts (DSP, oscilloscope, pulser/receiver, digitizer), scanner, and control program. The developed system has been applied to a practical ultrasonic testing in overlay weld, and demonstrated high speed with precision

• Journal of Korea Multimedia Society
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• v.14 no.10
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• pp.1275-1286
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• 2011

This paper proposes a high speed systolic array architecture for full search block matching algorithm (FBMA). The pixels of the search area for a reference block are input only one time to find the matched candidate block and reused to compute the sum of absolute difference (SAD) for the adjacent candidate blocks. Each row of designed 2-dimensional systolic array compares the reference block with the adjacent blocks of the same row in search area. The lower rows of the designed array get the pixels from the upper row and compute the SAD with reusing the overlapped pixels of the candidate blocks within same column of the search area. This designed array has no data broadcasting and global paths. The comparison with existing architectures shows that this array is superior in terms of throughput through it requires a little more hardware.

• ETRI Journal
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• v.24 no.5
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• pp.391-397
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• 2002

This paper presents digital signal processor (DSP) instructions and their data processing unit (DPU) architecture for high-speed fast Fourier transforms (FFTs) in orthogonal frequency division multiplexing (OFDM) systems. The proposed instructions jointly perform new operation flows that are more efficient than the operation flow of the multiply and accumulate (MAC) instruction on which existing DSP chips heavily depend. We further propose a DPU architecture that fully supports the instructions and show that the architecture is two times faster than existing DSP chips for FFTs. We simulated the proposed model with a Verilog HDL, performed a logic synthesis using the 0.35 ${\mu}m$ standard cell library, and then verified the functions thoroughly.