• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.195-198
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• 2000

It is possible to perform the digital fuzzy logical high-speed and high-precision computation by the use of redundantly-represented binary positive-digit number arithmetic operation. In this paper, as basic operation circuits in the fuzzy logic new voltage-mode 4-valued binary parallel processing operation circuits using positive redundantly-expressed binary-coded numbers is discussed.

• Proceedings of the IEEK Conference
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• 2007.07a
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• pp.85-86
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• 2007

In this paper, a Radix-8 structure for high-speed FFT is proposed. Even throughput of the Radix-8 FFT is twice than that of the Radix-4 FFT, implementation area of the Radix-8 is larger than that of Radix-4 FFT. But, implementation area of the proposed Radix-8 FFT was reduced by using DA(Distributed Arithmetic) for multiplication. The Verilog-HDL coding results for the proposed FFT structure show 49.2% cell area increment comparison with those of the conventional Radix-4 FFT structure. Namely, to speed up twice, 49.2% of area cost is required. In case of same throughput, power consumption of the proposed structure is reduced by 25.4%.

• Proceedings of the Korea Multimedia Society Conference
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• 2003.05b
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• pp.14-18
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• 2003

This paper presents the pipeline architecture for the low and column address generator of 2D DCT/IDCT(Discrete Cosine Transform/Inverse Discrete Cosine Transform). For the real time process of image data, it is required that high speed operation and small size hardware In the proposed architecture, the area of hardware is reduced by using the DA(distributed arithmetic) method and applying the concepts of pipeline on the parallel architecture. As a results, the designed pipeline of the low and column address generator for 2D DCT/IDCT architecture is implemented with an efficiency and high speed compared as the non-pipeline architecture. And the operation speed is improved about 50％ up. The design for the proposed pipeline architecture of DCT/IDCT is coded using VHDL.

• Progress in Superconductivity
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• v.6 no.2
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• pp.104-107
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• 2005

We have developed and tested an RSFQ 4-bit Arithmetic Logic Unit (ALU) based on half adder cells and de switches. ALU is a core element of a computer processor that performs arithmetic and logic operations on the operands in computer instruction words. The designed ALU had limited operation functions of OR, AND, XOR, and ADD. It had a pipeline structure. We have simulated the circuit by using Josephson circuit simulation tools in order to reduce the timing problem, and confirmed the correct operation of the designed ALU. We used simulation tools of $XIC^{TM},\;WRspice^{TM}$, and Julia. The fabricated 4-bit ALU circuit had a size of $\3000{\ cal}um{\times}1500{\cal}$, and the chip size was $5{\cal} mm{\times}5{\cal}mm$. The test speeds were 1000 kHz and 5 GHz. For high-speed test, we used an eye-diagram technique. Our 4-bit ALU operated correctly up to 5 GHz clock frequency. The chip was tested at the liquid-helium temperature.

• Progress in Superconductivity
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• v.7 no.2
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• pp.109-113
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• 2006

The Arithmetic Logic Unit (ALU) is a core element of a computer processor that performs arithmetic and logic operations on the operands in computer instruction words. We have developed and tested an RSFQ multi-bit ALU constructed with half adder unit cells. To reduce the complexity of the ALU, We used half adder unit cells. The unit cells were constructed of one half adder and three de switches. The timing problem in the complex circuits has been a very important issue. We have calculated the delay time of all components in the circuit by using Josephson circuit simulation tools of XIC, $WRspice^{TM}$, and Julia. To make the circuit work faster, we used a forward clocking scheme. This required a careful design of timing between clock and data pulses in ALU. The designed ALU had limited operation functions of OR, AND, XOR, and ADD. It had a pipeline structure. The fabricated 1-bit, 2-bit, and 4-bit ALU circuits were tested at a few kilo-hertz clock frequency as well as a few tens giga-hertz clock frequency, respectively. For high-speed tests, we used an eye-diagram technique. Our 4-bit ALU operated correctly at up to 5 GHz clock frequency.

• Smart Structures and Systems
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• v.14 no.6
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• pp.1131-1150
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• 2014

One of the issues in extending the range of applicable problems of real-time hybrid simulation is the computation speed of the simulator when large-scale computational models with a large number of DOF are used. In this study, functionality of real-time dynamic simulation of MDOF systems is achieved by creating a logic circuit that performs the step-by-step numerical time integration of the equations of motion of the system. The designed logic circuit can be implemented to an FPGA-based system; FPGA (Field Programmable Gate Array) allows large-scale parallel computing by implementing a number of arithmetic operators within the device. The operator splitting method is used as the numerical time integration scheme. The logic circuit consists of blocks of circuits that perform numerical arithmetic operations that appear in the integration scheme, including addition and multiplication of floating-point numbers, registers to store the intermediate data, and data busses connecting these elements to transmit various information including the floating-point numerical data among them. Case study on several types of linear and nonlinear MDOF system models shows that use of resource sharing in logic synthesis is crucial for effective application of FPGA to real-time dynamic simulation of structural response with time step interval of 1 ms.

• Journal of information and communication convergence engineering
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• v.12 no.3
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• pp.145-153
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• 2014

The improvements of embedded processors make future technologies including wireless sensor network and internet of things feasible. These applications firstly gather information from target field through wireless network. However, this networking process is highly vulnerable to malicious attacks including eavesdropping and forgery. In order to ensure secure and robust networking, information should be kept in secret with cryptography. Well known approach is public key cryptography and this algorithm consists of finite field arithmetic. There are many works considering high speed finite field arithmetic. One of the famous approach is Montgomery multiplication. In this study, we investigated Montgomery multiplication for public key cryptography on embedded microprocessors. This paper includes helpful information on Montgomery multiplication implementation methods and techniques for various target devices including 8-bit and 16-bit microprocessors. Further, we expect that the results reported in this paper will become part of a reference book for advanced Montgomery multiplication methods for future researchers.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.28B no.7
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• pp.520-534
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• 1991

This paper describes the design of an ALU and a shifter for RISC. The RISC datapath is designed to have a 4-stage pipeline and a 20 MHz operating frequency. The ALU makes use of the 32-bit BLC adder which has the characteristics of high speed ane regular structuer and executes the arithmetic instructions-addition and subtraction- and the logical instructions-AND, OR, and XOR. Additionally, multiplication is possible by iterative executions of step instructions to perform shift and add operations. The shifter is implemented by using the modified of funnel shifter. The shifter is able to perform the arithmetic andlogical shift instructions without maskiog. Moreover, it carries out data align operation which conforms to big endian byte address. The logical operation of the desinged ALU and the shifter were simulated using YSLOG and VLSIsim. SPICE simulation results using 1.2um double metal process parameters show that the ALU and shifter have a delay time of 15.9NS and 9.9NS, respectively. Therefore, the ALU and the shifter operates correctly above 20[ MHz ] click ferquency and are composed of about 7K and 15K teansistors, respectively.

• Journal of the Optical Society of Korea
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• v.9 no.3
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• pp.111-118
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• 2005

In this paper, a new optical parallel binary arithmetic processor (OPBAP) capable of computing arbitrary n-bit look-ahead carry full-addition is proposed and implemented. The conventional Boolean algebra is considered to implement OPBAP by using two schemes of optical logic processor. One is space-variant optical logic gate processor (SVOLGP), the other is shadow-casting optical logic array processor (SCOLAP). SVOLGP can process logical AND and OR operations different in space simultaneously by using free-space interconnection logic filters, while SCOLAP can perform any possible 16 Boolean logic function by using spatial instruction-control filter. A dual-rail encoding method is adopted because the complement of an input is needed in arithmetic process. Experiment on OPBAP for an 8-bit look-ahead carry full addition is performed. The experimental results have shown that the proposed OPBAP has a capability of optical look-ahead carry full-addition with high computing speed regardless of the data length.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.29 no.3
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• pp.511-514
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• 2019

Elliptic Curves Cryptosystem(ECC) provides the same level of security with relatively small key sizes, as compared to the traditional cryptosystems. The performance of ECC over GF(2m) and GF(p) depends on the efficiency of finite field arithmetic, especially the modular multiplication which is based on the reduction algorithm. In this paper, we propose a new modular reduction algorithm which provides high-speed ECC over NIST prime P-256. Detailed experimental results show that the proposed algorithm is about 25% faster than the previous methods.