• 한국진공학회:학술대회논문집
• /
• 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
• /
• pp.344-344
• /
• 2014

Transparent amorphous oxide semiconductors such as a In-Ga-Zn-O (a-IGZO) have advantages for large area electronic devices; e.g., uniform deposition at a large area, optical transparency, a smooth surface, and large electron mobility >10 cm2/Vs, which is more than an order of magnitude larger than that of hydrogen amorphous silicon (a-Si;H).1) Thin film transistors (TFTs) that employ amorphous oxide semiconductors such as ZnO, In-Ga-Zn-O, or Hf-In-Zn-O (HIZO) are currently subject of intensive study owing to their high potential for application in flat panel displays. The device fabrication process involves a series of thin film deposition and photolithographic patterning steps. In order to minimize contamination, the substrates usually undergo a cleaning procedure using deionized water, before and after the growth of thin films by sputtering methods. The devices structure were fabricated top-contact gate TFTs using the a-IGZO films on the plastic substrates. The channel width and length were 80 and 20 um, respectively. The source and drain electrode regions were defined by photolithography and wet etching process. The electrodes consisting of Ti(15 nm)/Al(120 nm)/Ti(15nm) trilayers were deposited by direct current sputtering. The 30 nm thickness active IGZO layer deposited by rf magnetron sputtering at room temperature. The deposition condition is as follows: a rf power 200 W, a pressure of 5 mtorr, 10% of oxygen [O2/(O2+Ar)=0.1], and room temperature. A 9-nm-thick Al2O3 layer was formed as a first, third gate insulator by ALD deposition. A 290-nm-thick SS6908 organic dielectrics formed as second gate insulator by spin-coating. The schematic structure of the IGZO TFT is top gate contact geometry device structure for typical TFTs fabricated in this study. Drain current (IDS) versus drain-source voltage (VDS) output characteristics curve of a IGZO TFTs fabricated using the 3-layer gate insulator on a plastic substrate and log(IDS)-gate voltage (VG) characteristics for typical IGZO TFTs. The TFTs device has a channel width (W) of $80{\mu}m$ and a channel length (L) of $20{\mu}m$. The IDS-VDS curves showed well-defined transistor characteristics with saturation effects at VG>-10 V and VDS>-20 V for the inkjet printing IGZO device. The carrier charge mobility was determined to be 15.18 cm^2 V-1s-1 with FET threshold voltage of -3 V and on/off current ratio 10^9.

• 대한전자공학회논문지SD
• /
• 제46권1호
• /
• pp.98-106
• /
• 2009

본 논문에서는 ultra mobile PC (UMPC) 및 휴대용 기기 시스템 같이 고속으로 동작하며 고해상도 저전력 및 소면적을 동시에 요구하는 16M-color low temperature Poly silicon (LTPS) thin film transistor liquid crystal display (TFT-LCD) 응용을 위한 1:12 MUX 기반의 1280-RGB $\times$ 800-Dot 70.78mW 0.13um CMOS LCD driver IC (LDI) 를 제안한다. 제안하는 LDI는 저항 열 구조를 사용하여 고해상도에서 전력 소모 및 면적을 최적화하였으며 column driver는 LDI 전체 면적을 최소화하기 위해 하나의 column driver가 12개의 채널을 구동하는 1:12 MUX 구조로 설계하였다. 또한 신호전압이 rail-to-rail로 동작하는 조건에서 높은 전압 이득과 낮은 소비전력을 얻기 위해 class-AB 증폭기 구조를 사용하였으며 고화질을 구현하기 위해 오프 셋과 출력편차의 영향을 최소화하였다 한편, 최소한의 MOS 트랜지스터 소자로 구현된 온도 및 전원전압에 독립적인 기준 전류 발생기를 제안하였으며, 저전력 설계를 위하여 차세대 시제품 칩의 source driver에 적용 가능한 새로운 구조의 slew enhancement기법을 추가적으로 제안하였다. 제안하는 시제품 LDI는 0.13um CMOS 공정으로 제작되었으며, 측정된 source driver 출력 정착 시간은 high에서 low 및 low에서 high 각각 1.016us, 1.072us의 수준을 보이며, source driver출력 전압 편차는 최대 11mV를 보인다. 시제품 LDI의 칩 면적은 $12,203um{\times}1500um$이며 전력 소모는 1.5V/5.5V 전원 저압에서 70.78mW이다.

• 한국세라믹학회지
• /
• 제39권12호
• /
• pp.1128-1132
• /
• 2002

MFS-FET(Metal-Ferroelectric-Semiconductor Field Effect Transistor) 구조의 비휘발성 기억소자용 $ReMnO_3$(Re:Y, Ho, Er) 박막을 금속 유기 화학 기상 증착법(MOCVD)으로 증착하였다. $ReMnO_3$ 박막을 Si(100) 기판 위에 700${\circ}C$-2시간 증착 시켜 결정화를 위해 대기 중에서 900${\circ}C$-1시간 열처리 시 육방정계(hexagonal) 단일상의 $ReMnO_3$ 박막을 형성하였다. 육방정계 단일상 구조에서 $ReMnO_3$ 박막의 강유전 특성은 c-축 배향성에 의존하였으며, c-축 배향성이 우수한 $YMnO_3$ 박막의 잔류 분극(Pr) 값은 105 nC/$cm^2$로 가장 우수하였다. 또한 누설 전류 밀도(leakage current density) 값은 미세구조의 결정립 크기에 의존하였으며, 결정립 크기가 100∼150 nm인 $YMnO_3$ 박막의 누설 전류 밀도 값은 인가전압 0.5 V에서 $10^{-8}$ A/$cm^2$을 나타내었다.

• 조명전기설비학회논문지
• /
• 제20권8호
• /
• pp.6-14
• /
• 2006

본 논문은 TFT-LCD(Thin Film Transistor Liquid Crystal Display) PECVD(Plasma Enhanced Chemical Vapor Deposition) 장비 공정용 챔버(Chamber) 세정을 위한 새로운 플라즈마 세정방법에 적합한 플라즈마 발생방법과 플라즈마 발생을 위한 고주파 전원장치의 전력회로에 관한 연구이다. 세정에 요구되는 고밀도 플라즈마는 안테나 형태의 기존 ICP(Inductively Coupled Plasma) 방식에 강자성체인 페라이트 코어를 적용하므로 써 $1{\times}10^{11}[EA/cm^3]$이상의 고밀도 플라즈마 발생을 가능하게 하였다. 플라즈마 발생을 위한 400[kHz] 고주파 전력 변환장치의 경우 범용 HB(Half Bridge) 인버터 방식을 적용하여 플라즈마 부하에서도 안정적인 영전압 스위칭 동작을 확인 하였다. 변압기 직렬결합 방식을 사용한 10[kW] 고출력을 통해 $A_r$과 $NF_3$가스 분위기하에서 플라즈마의 밀도와 $NF_3$가스 분해율을 측정하므로서 고주파 전력 변환 장치의 성능을 입증하였다.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2009년도 추계학술대회 논문집
• /
• pp.5-5
• /
• 2009

Thin-film-transistors (TFTs) that can be prepared at low temperatures have attracted much attention because of the great potential for transparent and flexible electronics. One of the mainstreams in this field is the use of organic semiconductors such as pentacene. But device performance of the organic TFTs is still limited due to low field-effect mobility and rapid degradation after exposing to air. Alternative approach is the use of amorphous oxide semiconductors as a channel. Amorphous oxide semiconductors (AOSs) based TFTs showed the fast technological development, because AOS films can be fabricated at room temperature and exhibit the possibility in application like flexible display, electronic paper, and larges solar cells. Among the various AOSs, a-IGZO has lots of advantages because it has high channel mobility, uniform surface roughness and good transparency. [1] The high mobility is attributed to the overlap of spherical s-orbital of the heavy post-transition metal cations. This study demonstrated the effect of the variation in channel thickness from 30nm to 200nm on the TFT device performance. When the thickness was increased, turn-on voltage and subthreshold swing was decreased. The a-IGZO channels and source/drain metals were deposited with shadow mask. The a-IGZO channel layer was deposited on $SiO_2$/p-Si substrates by RF magnetron sputtering, where RF power is 150W. And working pressure is 3m Torr, at $O_2/Ar$ (2/28 sccm) atmosphere. The electrodes were formed with electron-beam evaporated Ti (30 nm) and Au (70 nm) bilayer. Finally, Al (150nm) as a gate metal was thermal-evaporated. TFT devices were heat-treated in a furnace at 250 $^{\circ}C$ and nitrogen atmosphere for 1hour. The electrical properties of the TFTs were measured using a probe-station. The TFT with channel thickness of 150nm exhibits a good subthreshold swing (SS) of 0.72 V/decade and on-off ratio of $1{\times}10^8$. The field effect mobility and threshold voltage were evaluated as 7.2 and 8 V, respectively.

• 한국진공학회:학술대회논문집
• /
• 한국진공학회 2010년도 제39회 하계학술대회 초록집
• /
• pp.169-169
• /
• 2010

As display industry requires various applications for future display technology, which can guarantees high level of flexibility and transparency on display panel, oxide semiconductor materials are regarded as one of the best candidates. $InGaZnO_4$(IGZO) has gathered much attention as a post-transition metal oxide used in active layer in thin-film transistor. Due to its high mobility fabricated at low temperature fabrication process, which is proper for application to display backplanes and use in flexible and/or transparent electronics. Electrical performance of amorphous oxide semiconductors depends on the resistance of the interface between source/drain metal contact and active layer. It is also affected by sheet resistance on IGZO thin film. Controlling contact/sheet resistance has been a hot issue for improving electrical properties of AOS(Amorphous oxide semiconductor). To overcome this problem, post-annealing has been introduced. In other words, through post-annealing process, saturation mobility, on/off ratio, drain current of the device all increase. In this research, we studied on the relation between device's resistance and post-annealing temperature. So far as many post-annealing effects have been reported, this research especially analyzed the change of electrical properties by increasing post-annealing temperature. We fabricated 6 main samples. After a-IGZO deposition, Samples were post-annealed in 5 different temperatures; as-deposited, $100^{\circ}C$, $200^{\circ}C$, $300^{\circ}C$, $400^{\circ}C$ and $500^{\circ}C$. Metal deposition was done on these samples by using Mo through E-beam evaporation. For analysis, three analysis methods were used; IV-characteristics by probe station, surface roughness by AFM, metal oxidation by FE-SEM. Experimental results say that contact resistance increased because of the metal oxidation on metal contact and rough surface of a-IGZO layer. we can suggest some of the possible solutions to overcome resistance effect for the improvement of TFT electrical performances.

• 한국정보디스플레이학회:학술대회논문집
• /
• 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
• /
• pp.421-427
• /
• 2009

We successfully fabricated 4.7-inch organic thin film transistors array with $640{\times}480$ pixels on flexible substrate. All the processes were done by photolithography, spin coating and ink-jet printing. The OTFT-Electrophoretic (EP) pixel structure, based on a top gate OTFT, was fabricated. The mobility, ON/OFF ratio, subthreshold swing and threshold voltage of OTFT on flexible substrate are: 0.01 ^2/V-s, 1.3 V/dec, 10E5 and -3.5 V. After laminated the EP media on OTFT array, a panel of 4.7-inch $640{\times}480$ OTFT-EPD was fabricated. All of process temperature in OTFT-EPD is lower than $150^{\circ}C$. The pixel size in our panel is $150{\mu}m{\times}150{\mu}m$, and the aperture ratio is 50 %. The OTFT channel length and width is 20 um and 200um, respectively. We also used OTFT to drive EP media successfully. The operation voltages that are used on the gate bias are -30 V during the row data selection and the gate bias are 0 V during the row data hold time. The data voltages that are used on the source bias are -20 V, 0 V, and 20 V during display media operation.

• 한국진공학회지
• /
• 제17권5호
• /
• pp.435-441
• /
• 2008

본 논문은 TIPS Pentacene을 유기반도체로 사용한 유기박막 트랜지스터의 용제에 따른 전기적 특성에 대한 연구로서, 용제로는 chlorobenzene, p-xylene, chloroform, toluene을 사용하였으며, 회전 도포 방법을 사용하여 TIPS pentacene을 혼합하여 적층하였다. chlorobenzene을 사용하여 만들어진 유기박막 트랜지스터는 $1.0{\times}10^{-2}cm^2/V{\cdot}s$의 전계효과 이동도, $4.3{\times}10^3$의 on/off 비율, 5.5 V의 문턱전압의 특성을 보였다. 반대로, chloroform을 사용하여 만들어진 유기박막 트랜지스터는 $5.8{\times}10^{-7}cm^2/V{\cdot}s$의 전계효과 이동도, $1.1{\times}10^2$의 on/off 비율, 1.7 V의 문턱전압의 특성을 보였다. 또한 각 용제에 따른 TIPS pentacene 결정크기를 AFM을 통하여 측정하였다. 이와 같은 결과들을 통하여, 더 높은 끊는점을 가진 용제는 TIPS Pentacene의 더 큰 결정 크기와 높은 결정화 성향으로 인하여 더 좋은 전기적 특성을 가지는 것을 확인할 수 있었으며, 본 실험에서는 끓는점이 가장 높은 chlorobenzene을 사용한 TIPS Pentacene 유기박막 트랜지스터가 가장 좋은 전기적 특성을 나타내는 것을 확인하였다.

• 센서학회지
• /
• 제29권4호
• /
• pp.266-269
• /
• 2020

In this study, we investigated the effect of a sulfur passivation (S-passivation) process step on the electrical properties of surface-channel In_0.7Ga_0.3As quantum-well (QW) metal-oxide-semiconductor field-effect transistors (MOSFETs) with S/D regrowth contacts. We fabricated long-channel In_0.7Ga_0.3As QW MOSFETs with and without (NH₄)₂S treatment and then deposited 1/4 nm of Al₂O₃/HfO₂ through atomic layer deposition. The devices with S-passivation exhibited lower values of subthreshold swing (74 mV/decade) and drain-induced barrier lowering (19 mV/V) than the devices without S-passivation. A conductance method was applied, and a low value of interface trap density D_it (2.83×10¹² cm^-2eV^-1) was obtained for the devices with S-passivation. Based on these results, interface traps between InGaAs and high-κ are other defect sources that need to be considered in future studies to improve III-V microsensor sensing platforms.

• 한국전자파학회논문지
• /
• 제17권3호
• /
• pp.239-248
• /
• 2006

본 논문에서는 pHEMT(pseudo-morphic High Electron Mobility Transistor)로 구성된 저잡음 증폭기 MMIC(Monolithic Microwave Integrated Circuit)를 이용하여 극저온에서 동작하는 전파 망원경 수신기 전단부용 22 GH2 대역 저잡음 증폭기 모듈을 설계, 제작하였다. pHEMT MMIC 선정에는, 극저온에서의 동작이 입증된 pHEMT 공정을 사용하여 제작된 저잡음 증폭기 MMIC를 선택하였다. 선정된 2개의 MMIC는 박막(thin film) 세라믹 기판에 장착하여 모듈화 하였다. 모듈화 시 하우징(housing)과 캐리어(carrier) 사이의 간극을 제거하고 전파 흡수체를 사용하여 불필요한 구조에 의한 발진을 제거하였다. 또한 커넥터와 기판 사이의 부정합으로 나타나는 잡음 및 이득의 열화를 리본 조정을 통해 개선시켜 상온에서 최적의 성능을 가지도록 했다. 제작된 증폭기 모듈은 상온에서 $21.5{\sim}23.5GHz$ 대역 내 이득 $35dB{\pm}1dB$, 잡음지수 $2.37{\sim}2.57dB$를 보였다. 제작된 증폭기는 헬륨 냉각기를 이용하여 $15^{\circ}K$로 냉각 후 측정 결과, 대역 내에서 이득 35 dB 이상, 잡음온도 $28{\sim}37^{\circ}K$를 얻었다.