• Journal of Electrical Engineering and Technology
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• v.10 no.5
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• pp.2040-2045
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• 2015

This paper deals with the electromagnetic and thermal analysis of high speed induction motor. The induction motor is analyzed by time-varying magnetic finite element method and its thermal analysis is carried out by using analytical lumped-circuit method. Analysis results are compared with the experiment of 29kW high speed motor prototype at 12,000rpm.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.7
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• pp.1-6
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• 2009

This paper presents new high speed architecture using DBI(Data Bus Inversion) in DRAM. The DBI is one of the general methods in the signaling circuits to decrease the known problems such as SSO and LSI. Many architectures have been proposed to reduce the number of transitions on the data bus. In this paper, the DBI, the Analog Majority Voter (AMV) circuit, the GIO control circuit and the SSO algorithm are newly proposed. The power consumption can he reduced with the help of direct GIO inversion method and the eye diagram of data can be increased to 40ps. Using proposed DBI scheme can produce almost stable SI of DQs against high speed operation. The DBI is fabricated in 90nm CMOS Technology.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.64 no.1
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• pp.7-13
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• 2015

This paper presents mathematical models for high speed permanent-magnet synchronous machine. The mathematical method with two successive steps is used to estimate design parameter as well as the output power. At first, mathematical model for a linkage flux problem is employed to calculate the number of winding turns and stack length of armature core. The magnetic circuit model for an induced voltage and the electric circuit model for a current are modeled. The output powers of the electrical generator were evaluated by the mathematical techniques. The results of this mathematical methods predict the specifications of the machine and can be applied in the design stage of the electrical machine.

• Journal of Institute of Control, Robotics and Systems
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• v.7 no.5
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• pp.399-406
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• 2001

This paper presents a dynamic modeling and a sliding mode controller for the high-speed/high-accuracy position control system. The selected target system is the wire bonder assembly which is used in the semiconductor assembly process. This system is a reciprocating one around the pivot point that consists of VCM(voice coil motor) as an actuator and transducer horn as a bonding tool. For the modeling elements, the sys-tem is divided into electrical circuit, magnetic circuit and mechanical system. Each system is modeled using the bond graph method and united into the full system. Two major aims are considered in the design of the controller. The first one is that the horn must track the given reference trajectory. The second one is that the controller must be realizable by using the DSP board. Computer simulation and experimental results show that the designed sliding mode controller provides better performance than the PID controller.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 2000.10a
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• pp.83-89
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• 2000

This paper presents a dynamic modeling and a sliding mode controller for the high-speed / high-accuracy position control system. Selected target system is the wire bonder head assembly which is used in semiconductor assembly process. This system is a reciprocating one around the pivot point that consists of VCM(voice coil motor) as a actuator and transducer horn as a bonding tool. For the modeling elements, the system is divided into electrical circuit, magnetic circuit and mechanical system. Each system is modeled by using the bond graph method and united into the full system. Two major aims are considered in the design of the controller. The first one is that the horn must track the given reference trajectory. The second one is that the controller must be realizable by using the DSP board. Computer simulation and experimental results show that the designed sliding mode controller provides better performance than the PID controller.

• Proceedings of the KIPE Conference
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• 2011.07a
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• pp.314-315
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• 2011

This paper introduces the design and control method of braking chopper circuit which can supply input power to ventilation inverter of traction control system. The DC input voltage from auxiliary block (static inverter) is normally used as an input of ventilation inverter. It converts DC input to AC output voltage to drive cooling fans for traction control system and traction motors. The electrical braking force is very important for high speed train to guarantee safety even though the train is running in the dead section where the pantograph voltage is not supplied. When the high speed train decelerate speed in dead section, the regenerative energy is dissipated by braking resistor. This paper proposed the braking chopper control method to implement rheostatic braking function and the appropriate chopper circuit for supplying voltage source to ventilation inverter during rheostatic braking mode. The proposed chopper circuit makes it possible for traction control system to regenerate power continuously regardless of the existence of pantograph voltage. The feasibility of proposed braking chopper control and circuit were proven by inertia load test and actual train field test.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.384-387
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• 1999

In this paper, we have proposed a testing methodology for Speed-Independent asynchronous control circuits using the self-checking property where the circuit detects certain classes of faults during normal operation. To exploit self-checking properties of Speed-Independent circuits, the Proposed methodology generates tests from the specification of the target circuit which describes the behavior of the circuit. The generated tests are applied to a fault-free and a faulty circuit, and target faults can be detected by the comparison of the outputs of the both circuits. For the purpose of efficient comparison, reachability information of the both circuits in the form of BDD's is used and operations are conducted by BDD manipulations. The identification for undetectable faults in testing is also used to increase efficiency of the proposed methodology. The proposed identification uses only topological information of the target circuit and reachability information of the good circuit which was generated in the course of preprocess. Experimental results show that high fault coverage is obtained for synthesized Speed-Independent circuits and the use of the identification process decreases the number of tests and execution time.

• Journal of Software Assessment and Valuation
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• v.15 no.1
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• pp.103-107
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• 2019

Recently, many technologies have been developed to realize low power high speed digital data communication and one of them is related to duty cycle correction. In this paper, a low-area duty cycle correction circuit for a voltage-controlled ring generator is proposed. The duty cycle correction circuit is a circuit that corrects the duty cycle using a 180 degree phase difference of a voltage controlled ring oscillator. The proposed low-area duty cycle circuit changes a conventional flip-flop to a true single phase clocking (TSPC) flip-flop And a low-area high-performance circuit is realized. By using TSPC flip-flop instead of general flip-flop, it is possible to realize low-area circuit compared to existing circuit, and it is expected to be used for high-performance circuit for low-power because it is easy to operate at high speed.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.657-658
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• 2006

A Novel level-shifter circuit for Display Panel Driver is presented. A Proposed level-shifter is for the high speed and high-voltage driving capability. In order to achieve this purpose, the proposed level-shifter restricts and separates the Vgs of the output driver's pull-up PMOS and pull-down NMOS with Zener diode. And a speed-up PMOS transistor is introduced to reduce delay. The control signal of speed-up PMOS was designed by bootstrapping method to minimize the gate to source (Vgs) voltage to avoid Vgs breakdown.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.4
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• pp.275-279
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• 2004

A new burst mode clock and data recovery circuit is realized that improves the previousldy-known gated-oscilletor technique with half rate clock recovery, The circuit was fabricated with 0.25um CMOS technology, and its functions were confirmed up to 1 Gbps.