• Journal of the Institute of Electronics Engineers of Korea SC
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• v.47 no.2
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• pp.25-34
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• 2010

This paper proposed a high-speed voltage-controlled ring-oscillator(VCRO) using a frequency doubling technique. The design of the proposed oscillator has been based on TSMC 0.18um 1.8V CMOS technology. The frequency doubling technique is achieved by AND-OR operations with 4 signals which have $90^{\circ}$ phase difference one another in one cycle. The proposed technique has been implemented using a 4-stage differential oscillator compose of differential latched inverters and NAND gates for AND and OR operations. The differential ring-oscillator can generate 4 output signals, which are $90^{\circ}$ out-of-phase one another, with low phase noise. The ANP-OR operations needed in the proposed technique are implemented using NAND gates, which is more area-efficient and provides faster switching speed than using NOR gates. Simulation results show that the proposed, VCRO operates in the frequency range of 3.72 GHz to 8 GHz with power consumption of 4.7mW at 4GHz and phase noise of ~-86.79dBc/Hz at 1MHz offset. Therefore, the proposed oscillator demonstrates superior performance compared with previous high-speed voltage-controlled ring-oscillators and can be used to build high-performance frequency synthesizers and phase-locked loops for radio-frequency applications.

• Journal of Biomedical Engineering Research
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• v.25 no.2
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• pp.137-144
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• 2004

ECG signals are often contaminated with high-frequency noise such as muscle artifact, power line interference, and others. In the ECG signal processing, especially during a pre-processing stage, numerous noise removal techniques have been used to reduce these high-frequency noise without much distorting the original signal. This paper proposes a new type of digital filter with a continuously variable cutoff frequency to improve the signal quality This filter consists of a cutoff frequency controller (CFC) and variable cutoff frequency lowpass filter (VCF-LPF). From the noisy input ECG signal, CFC produces a cutoff frequency control signal using the signal slew rate. We implemented VCF-LPF based on two new filter design methods called convex combination filter (CCF) and weight interpolation fille. (WIF). These two methods allow us to change the cutoff frequency of a lowpass filter In an arbitrary fine step. VCF-LPF shows an excellent noise reduction capability for the entire time segment of ECG excluding the rising and falling edge of a very sharp QRS complex. We found VCF-LPF very useful and practical for better signal visualization and probably for better ECG interpretation. We expect this new digital filter will find its applications especially in a home health management system where the measured ECG signals are easily contaminated with high-frequency noises .

• Journal of Internet Computing and Services
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• v.10 no.4
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• pp.87-103
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• 2009

Grid computing is an expanded technology of distributed computing technology to use low-cost and high-performance computing power in various fields. Although the purpose of Grid computing focuses on large-scale resource sharing, innovative applications, and in some case, high-performance orientation, it has been used as conventional distributed computing environment like clustered computer until now because Grid middleware does not have common sharable information system. In order to use Grid computing environment efficiently which consists of various Grid middlewares, it is necessary to have application-independent information system which can share information description and services, and expand them easily. Thus, in this paper, we propose a semantic information system framework based on web services and ontology for Grid computing environment, called WebSIS. It makes application and middleware developer easy to build sharable and extensible information system which is easy to share information description and can provide ontology based platform-independent information services. We present efficient ontology based information system architecture through WebSIS. Discovering appropriate resource for task execution on Grid needs more high-level information processing because Grid computing environment is more complex than other traditional distributed computing environments and has various considerations which are needed for Grid task execution. Thus, we design and implement resource information system and services by using WebSIS which enables high-level information processing by ontology reasoning and semantic-matching, for automation of task execution on Grid.

• Proceedings of the Materials Research Society of Korea Conference
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• 2012.05a
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• pp.68.1-68.1
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• 2012

The best part of graphene is - charge-carriers in it are mass less particles which move in near relativistic speeds. Comparing to other materials, electrons in graphene travel much faster - at speeds of $10^8cm/s$. A graphene sheet is pure enough to ensure that electrons can travel a fair distance before colliding. Electronic devices few nanometers long that would be able to transmit charge at breath taking speeds for a fraction of power compared to present day CMOS transistors. Many researches try to check a possibility to make it a perfect replacement for silicon based devices. Graphene has shown high potential to be used as interconnects in the field of high frequency electrical devices. With all those advantages of graphene, we demonstrate characteristics of electrical and optical properties of graphene such as the effect of graphene geometry on the microwave properties using the measurements of S-parameter in range of 500 MHz - 40 GHz at room temperature condition. We confirm that impedance and resistance decrease with increasing the number of graphene layer and w/L ratio. This result shows proper geometry of graphene to be used as high frequency interconnects. This study also presents the optical properties of graphene oxide (GO), which were deposited in different substrate, or influenced by oxygen plasma, were confirmed using different characterization techniques. 4-6 layers of the polycrystalline GO layers, which were confirmed by High resolution transmission electron microscopy (HRTEM) and electron diffraction analysis, were shown short range order of crystallization by the substrate as well as interlayer effect with an increase in interplanar spacing, which can be attributed to the presence of oxygen functional groups on its layers. X-ray photoelectron Spectroscopy (XPS) and Raman spectroscopy confirms the presence of the $sp^2$ and $sp^3$ hybridization due to the disordered crystal structures of the carbon atoms results from oxidation, and Fourier Transform Infrared spectroscopy (FTIR) and XPS analysis shows the changes in oxygen functional groups with nature of substrate. Moreover, the photoluminescent (PL) peak emission wavelength varies with substrate and the broad energy level distribution produces excitation dependent PL emission in a broad wavelength ranging from 400 to 650 nm. The structural and optical properties of oxygen plasma treated GO films for possible optoelectronic applications were also investigated using various characterization techniques. HRTEM and electron diffraction analysis confirmed that the oxygen plasma treatment results short range order crystallization in GO films with an increase in interplanar spacing, which can be attributed to the presence of oxygen functional groups. In addition, Electron energy loss spectroscopy (EELS) and Raman spectroscopy confirms the presence of the $sp^2$ and $sp^3$ hybridization due to the disordered crystal structures of the carbon atoms results from oxidation and XPS analysis shows that epoxy pairs convert to more stable C=O and O-C=O groups with oxygen plasma treatment. The broad energy level distribution resulting from the broad size distribution of the $sp^2$ clusters produces excitation dependent PL emission in a broad wavelength range from 400 to 650 nm. Our results suggest that substrate influenced, or oxygen treatment GO has higher potential for future optoelectronic devices by its various optical properties and visible PL emission.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.22 no.5
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• pp.310-316
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• 2021

Conventional satellites are generally large satellites that are multi-functional and have high performance. However, small satellites have been gradually drawing attention since the recent development of lightweight and integrated electric, electronic, and optical technologies. As the size and weight of a satellite decrease, the barrier to satellite development is becoming lower due to the cost of manufacture and cheaper launch. However, solar panels are essential for the power supply of satellites but have limitations in miniaturization and weight reduction because they require a large surface area to be efficiently exposed to sunlight. Space solar cells must be manufactured in consideration of various space environments such as spacecraft and environments with solar thermal temperatures. It is necessary to study structural materials for lightweight and high-efficiency solar cells by applying an unfolding mechanism that optimizes the surface-to-volume ratio. Currently, most products are developed and operated as solar cell panels for space applications with a triple-junction structure of InGaP/GaAs/Ge materials for high efficiency. Furthermore, multi-layered junctions have been studied for ultra-high-efficiency solar cells. Flexible thin-film solar cells and organic-inorganic hybrid solar cells are advantageous for material weight reduction and are attracting attention as next-generation solar cells for small satellites.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.60-68
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• 2009

This work proposes a 10b 200MS/s 65nm CMOS ADC for high-definition video systems such as HDTV requiring high resolution and fast operating speed simultaneously. The proposed ADC employs a four-step pipeline architecture to minimize power consumption and chip area. The input SHA based on four capacitors reduces the output signal range from $1.4V_{p-p}$ to $1.0V_{p-p}$ considering high input signal levels at a low supply voltage of 1.2V. The proposed three-stage amplifiers in the input SHA and MDAC1 overcome the low output resistance problem as commonly observed in a 65nm CMOS process. The proposed multipath frequency-compensation technique enables the conventional RNMC based three-stage amplifiers to achieve a stable operation at a high sampling rate of 200MS/s. The conventional switched-bias power-reduction technique in the sub-ranging flash ADCs further reduces power consumption while the reference generator integrated on chip with optional off-chip reference voltages allows versatile system a locations. The prototype ADC in a 65nm CMOS technology demonstrates a measured DNL and INL within 0.19LSB and 0.61LSB, respectively. The ADC shows a maximum SNDR of 54.BdB and 52.4dB and a maximum SFDR of 72.9dB and 64.8dB at 150MS/S and 200MS/s, respectively. The proposed ADC occupies an active die area of $0.76mm^2$ and consumes 75.6mW at a 1.2V supply voltage.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.75-85
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• 2009

This work proposes a 13b 100MS/s 0.13um CMOS ADC for 3G communication systems such as two-carrier W-CDMA applications simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs a four-step pipeline architecture to optimize power consumption and chip area at the target resolution and sampling rate. Area-efficient high-speed high-resolution gate-bootstrapping circuits are implemented at the sampling switches of the input SHA to maintain signal linearity over the Nyquist rate even at a 1.0V supply operation. The cascode compensation technique on a low-impedance path implemented in the two-stage amplifiers of the SHA and MDAC simultaneously achieves the required operation speed and phase margin with more reduced power consumption than the Miller compensation technique. Low-glitch dynamic latches in sub-ranging flash ADCs reduce kickback-noise referred to the differential input stage of the comparator by isolating the input stage from output nodes to improve system accuracy. The proposed low-noise current and voltage references based on triple negative T.C. circuits are employed on chip with optional off-chip reference voltages. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates the measured DNL and INL within 0.70LSB and 1.79LSB, respectively. The ADC shows a maximum SNDR of 64.5dB and a maximum SFDR of 78.0dB at 100MS/s, respectively. The ABC with an active die area of $1.22mm^2$ consumes 42.0mW at 100MS/s and a 1.2V supply, corresponding to a FOM of 0.31pJ/conv-step.

• The KIPS Transactions:PartA
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• v.16A no.6
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• pp.443-452
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• 2009

Although 32-bit architectures are becoming the norm for modern microprocessors, 16-bit ones are still employed by many low-end processors, for which small size and low power consumption are of high priority. However, 16-bit architectures have a critical disadvantage for embedded processors that they do not provide enough encoding space to add special instructions coined for certain applications. To overcome this, many existing architectures adopt non-orthogonal, irregular instruction sets to accommodate a variety of unusual addressing modes. In general, these non-orthogonal architectures are regarded compiler-unfriendly as they tend to requires extremely sophisticated compiler techniques for optimal code generation. To address this issue, we proposed a compiler-friendly processor with a new addressing mode, called the dynamic implied addressing mode(DIAM). In this paper, we will demonstrate that the DIAM provides more encoding space for our 16-bit processor so that we are able to support more instructions specially customized for our applications. And we will explain the advanced architecture which has improved performance. In our experiment, the proposed architecture shows 11.6% performance increase on average, as compared to the basic architecture.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07a
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• pp.489-492
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• 2005

We report new polymer stabilized ferroelectric liquid crystal (PSFLC) cells with mechanical stability which is achievable by introducing photospacers in the cells. It was found that the mechanical st ability of the PSFLC cell was effected by introduction of photo spacers. We analyzed the dependence of mechanical stability and memory property on the density of photospacers in the PSFLC cell. The stability and memory properties of PSFLC Cells depending on photospacer density are discussed. 1. Introduction Recently, flexible displays have attracted much attention because they have remarkable advantages: thinner, lighter, non-breakable and conformable features. Flexible displays have various potential applications such as e-book and e-paper displays utilizing the distinct features. E-book and E-paper displays demand very low power consumption, so that bistable memory liquid crystal modes are required in case of flexible plastic LCDs for those application. Three kinds of memory LC modes have been developed; bistable nematic, bistable cholesteric and bistable FLC. Among them SSFLC as one of bistable FLC has big advantages such as low driving voltage, wide view angle and fast response time, SSFLC cells are, however, very weak against mechanical shock. Polymer stabilized FLC (PSFLC) has been developed to overcome the poor mechanical stability of SSFLC. PSFLC was known to have network structure that FLCs are oriented with smectic layer ordering in polymer network. The polymer network stabilizes the FLC orientation, which leads to improvement of mechanical stability of PSFLCD. A lot of studies have been done for the application of PSFLC to flexible $LCDs.^{[1{\sim}12]}$ However, it should be noted that PSFLC does not have sufficient mechanical stability for the particular applications such as smart card LCD, where LCD is highly bendable.Bead spacer was mainly used to maintain cell gap of conventional PSFLCDs. But the spacer density of it is not locally uniform in the cell, so that it is generally difficult that the PSFLCDs with bead spacers show sufficient mechanical stability. In order to more improve the mechanical stability of PSFLCDs, we introduced photospacers into PSFLCDs. In this paper, we describe the improvement of mechanical stability by introducing photospacers into PSFLCDs.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.20 no.4
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• pp.164-167
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• 2010

Bulk GaN single crystal with 1.5 mm thickness was successfully grown by hydride vapor phase epitaxy (HVPE) technique. Free-standing GaN substrates of $10{\times}10,\;15{\times}15$ mm size were fabricate after lift-off of sapphire substrate and their optical properties were characterized properties for device applications. X-ray diffraction patterns showed (002) and (004) peak, and the FWHM of the X-ray rocking curve (XRC) measurement in (002) was 98 arcsec. A sharp photoluminescence spectrum at 363 nm was observed and defect spectrum at visible range was not detected. The hexagonal-shaped etch-pits are formed on the GaN surface in $200^{\circ}C\;H_3PO_4$ at 5 minutes. The defect density calculated from observed etch-pits on surface was around $5{\times}10^6/cm^2$. This indicates that the fabricated GaN substrates can be used for applications in the field of optodevice, and high power electronics.