• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.11 s.114
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• pp.1030-1039
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• 2006

A high power and high gain Doherty amplifier is designed by using embedded driver amplifiers in the final stage. The operational characteristics of a two-stage Doherty amplifier are analyzed, as a function of the two-stage peaking amplifier gate biases. The driver stages and final output stages are implemented using two single-ended MRF21045s and a single push-pull packaged MRF5P21180, respectively. This two-stage Doherty amplifier demonstrated 27 dB gain with a PAE of 23 % at 15 W average output power.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2005.11a
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• pp.81-86
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• 2005

In this paper, we present an efficiency extension of Doherty power amplifier using LDMOS FET devices with different peak output powers and an unequal power divider. The amplifier is designed by using a MRF21045 with P1 dB of 45 W as the main amplifier biased for Class-AB operation and a MRF21090 with P1 dB of 90 W as the peaking amplifier biased for Class-C operation. The input power is divided into a 1:1.5 power ratio between the main and peaking amplifier. The simulated results of the proposed Doherty amplifier shows an efficiency improvement of approximately 19 % in comparison to the class-AB amplifier at an output power of 42.5 dBm. The fabricated Doherty amplifier obtained a PAE of 33.68 % at 9 dB backed off from P1 dB of 51.5 dBm.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.26 no.11
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• pp.48-53
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• 2012

In this paper designed J-class amplifier that have high efficiency using parasitic of pHEMT. Measured results of the designed J-class amplifier is maxmum output power of 31.5dBm and gain of 16.5dB, minimum output power of 29.8dBm. when input power 15dBm. Maxmum drain efficiency is 76.2% at 2.95GHz, maxmum drain efficiency is 61%. The J-class amplifier has average gain of 15.35dB and average efficiency of 35%.

• The Journal of the Korea institute of electronic communication sciences
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• v.15 no.3
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• pp.421-432
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• 2020

This paper proposes a 2-kW solid-state power amplifier (SSPA) developed by employing power amplifier pallets designed using gallium-nitride high electron mobility transistors, which is used in S-band military radars and to replace existing traveling-wave tube amplifier (TWTA). The SSPA consists of a high-power amplifier module, which combines eight power amplifier pallets, a drive amplifier module, a digital control module, and a power supply unit. First, the amplifier module and component were integrated into a small package to account for space limitations; next, an on-board harmonic filter was fabricated to reject spurious components; and finally, an auto gain control system was designed for various duty ratios because recent military radar systems are all active phase radars using the pulse operation mode. The developed SSPA exhibited a max gain of 48 dB and an output power ranging between 63-63.6 dBm at a frequency band of 3.1 to 3.5 GHz. The auto gain control function showed that the output power is regulated around 63 dBm despite the fluctuation of the input power from 15-20 dBm. Finally, reliability of the developed system was verified through a temperature environment test for nine hours at high (55 ℃) / low (-40℃) temperature profile in accordance with military standard 810. The developed SSPA show better performance such as light weight, high output, high gain, various safety function, low repair cost and short repair time than existing TWTA.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.10 no.5
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• pp.71-78
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• 2011

In this paper, we describe the design and implementation of a high efficiency and broad-band Class-J mode power amplifier using gallium nitride(GaN) high-electron mobility transistor(HEMT). The matching circuit of proposed class-J mode power amplifier for 2nd harmonic impedance designed to provide pure reactance alone. The measurement results show that output power of $40{\pm}1$ dBm, power-added efficiency of 50%, and drain efficiency of 60% for a continuous wave signal at 1.4 to 2.6 GHz.

• ETRI Journal
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• v.19 no.2
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• pp.35-47
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• 1997

A power amplifier operating at 3.3 V has been developed for CDMA/AMPS dual-mode cellular phones. It consists of linear GaAs power MESFET's, a new gate bias control circuit, and an output matching circuit which prevents the drain terminal of the second MESF from generating the harmonics. The relationship between the intermodulation distortion and the spectral regrowth of the power amplifier has been investigated with gate bias by using the two-tone test method and the adjacent channel leakage power ratio (ACPR) method of CDMA signals. The dissipation power of the power amplifier with a gate bias control circuit is minimized to below 1000 mW in the range of the low power levels while satisfying the ACPR of less than -26 dBc for CDMA mode. The ACPR of the power amplifier is measured to be -33 dBc at a high output power of 26 dBm.

• ETRI Journal
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• v.39 no.5
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• pp.737-745
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• 2017

A 6-GHz-to-18-GHz monolithic nonuniform distributed power amplifier has been designed using the load modulation of increased series gate capacitance. This amplifier was implemented using a $0.25-{\mu}m$ AlGaN/GaN HEMT process on a SiC substrate. With the proposed load modulation, we enhanced the amplifier's simulated performance by 4.8 dB in output power, and by 13.1% in power-added efficiency (PAE) at the upper limit of the bandwidth, compared with an amplifier with uniform gate coupling capacitors. Under the pulse-mode condition of a $100-{\mu}s$ pulse period and a 10% duty cycle, the fabricated power amplifier showed a saturated output power of 39.5 dBm (9 W) to 40.4 dBm (11 W) with an associated PAE of 17% to 22%, and input/output return losses of more than 10 dB within 6 GHz to 18 GHz.

• ETRI Journal
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• v.33 no.5
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• pp.679-688
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• 2011

A new discrete-amplitude pulse width modulation (DAPWM) scheme for a high-efficiency linear power amplifier is proposed. A radio frequency (RF) input signal is divided into an envelope and a phase modulated carrier. The low-frequency envelope is modulated so that it can be represented by a pulse whose area is proportional to its amplitude. The modulated pulse has at least two different pulse amplitude levels in order that the duty ratios of the pulse are kept large for small input. Then, an RF pulse train is generated by mixing the modulated envelope with the phase modulated carrier. The RF pulse train is amplified by a switching-mode power amplifier, and the original RF input signal is restored by a band pass filter. Because duty ratios of the RF pulse train are kept large in spite of a small input envelope, the DAPWM technique can reduce loss from harmonic components. Furthermore, it reduces filtering efforts required to suppress harmonic components. Simulations show that the overall efficiency of the pulsed power amplifier with DAPWM is about 60.3% for a mobile WiMax signal. This is approximately a 73% increase compared to a pulsed power amplifier with PWM.

• Journal of IKEEE
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• v.14 no.2
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• pp.90-97
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• 2010

The high efficiency power management IC(PMIC) with DTMOS(Dynamic Threshold voltage MOSFET) switching device and DTMOS Error Amplifier is presented in this paper. PMIC is controlled with PWM control method in order to have high power efficiency at high current level. Dynamic Threshold voltage CMOS(DT-CMOS) with low on-resistance is designed to decrease conduction loss. The control parts in Buck converter, that is, PWM control circuits consist of a saw-tooth generator, a band-gap reference circuit, an DT-CMOS error amplifier and a comparator circuit as a block. the proposed DT-CMOS Error Amplifier has 72dB DC gain and 83.5deg phase margin. also Error Amplifier that use DTMOS more than CMOS showed power consumption decrease of about 30%. DC-DC converter, based on Voltage-mode PWM control circuits and low on-resistance switching device is achieved the high efficiency near 96% at 100mA output current. And DC-DC converter is designed with Low Drop Out regulator(LDO regulator) in stand-by mode which fewer than 1mA for high efficiency.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.17 no.4
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• pp.116-125
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• 2003

According to the recent developments of computer, terrestrial broadcasting, satellite broadcasting and CATV technologies, Multimedia TV application combined with such technologies will emerge. Therefore, it is demanded that high-power, wide-band, and high-frequency performance. In this paper, HPA(high power amplifier) for digital TV transmission system is proposed. The analysis and evaluation on the proposed amplifier have been performed by 2-tone signal for general performance evaluation and by 8-VSB signal for comparison with real system. In result, proposed HPA satisfies requirements of high-power, wide-band, and high-frequency performance.