• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.5 s.120
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• pp.553-562
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• 2007

In this paper, we designed and implemented the system for telemetering ELF(Extremely Low Frequency) magnetic field intensity. The magnetic field measurement system used a 3-axis magnetic field sensor to measure the magnetic field with isotropy and the equalizer to compensate the frequency characteristic in band. By multiplexing three output signals of the magnetic field sensor in time domain, we got the uniform gain and frequency characteristic among three axes. This system was designed that the magnetic field measurement level range was $0.01{\sim}10.0\;uT$ and the measurement frequency band was $40{\sim}180\;Hz$. The control system would access to the magnetic field measurement system with RF and the maximum access distance was 1.0 km. We confirmed that the measurement level error of the fabricated system was within 5 %. The fabricated system was installed to a golf practice range where a high voltage power transmission line was crossed.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.15 no.3
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• pp.57-66
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• 2001

This paper resents a control approach for designing a fuzzy-PI controller for a synchronous generator excitation and SVC system A combination of thyristor-controlled reactors and fixed capacitors (TCR-FC) type SVC is recognized as having the must fiexible control and high speed response, which has been widely utilized in power systems, is considered and designed to improve the response of a synchronous generator, as well as controlling the system voltage A Fuzzy-PI controller for SVC system was proposed in this paper. The PI gain parameters of the proposed Fuzzy-PI controller which is a special type of PI ones are self-tuned by fuzzy inference technique. It is natural that the fuzzy inference technique should be barred on humans intuitions and empirical knowledge. Nonetheless, the conventional ones were not so. Therefore, In this paper, the fuzzy inference technique of PI gains using MMGM(Min Max Gravity Method) which is very similar to humans inference procedures, was presented and allied to the SVC system. The system dynamic responses are examined after applying all small disturbance condition.

• Korean Journal of Materials Research
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• v.29 no.10
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• pp.586-591
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• 2019

This study describes the doping effect of $Yb_2O_3$ on microstructure, electrical and dielectric properties of $ZnO-V_2O_5-MnO_2-Nb_2O_5$ (ZVMN) ceramic semiconductors sintered at a temperature as low as $900^{\circ}C$. As the doping content of $Yb_2O_3$ increases, the ceramic density slightly increases from 5.50 to $5.54g/cm^3$; also, the average ZnO grain size is in the range of $5.3-5.6{\mu}m$. The switching voltage increases from 4,874 to 5,494 V/cm when the doping content of $Yb_2O_3$ is less than 0.1 mol%, whereas further doping decreases this value. The ZVMN ceramic semiconductors doped with 0.1 mol% $Yb_2O_3$ reveal an excellent nonohmic coefficient as high as 70. The donor density of ZnO gain increases in the range of $2.46-7.41{\times}10^{17}cm^{-3}$ with increasing doping content of $Yb_2O_3$ and the potential barrier height and surface state density at the grain boundaries exhibits a maximum value (1.25 eV) at 0.1 mol%. The dielectric constant (at 1 kHz) decreases from 592.7 to 501.4 until the doping content of $Yb_2O_3$ reaches 0.1 mol%, whereas further doping increases it. The value of $tan{\delta}$ increases from 0.209 to 0.268 with the doping content of $Yb_2O_3$.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.22 no.4
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• pp.67-72
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• 2022

This study presents the design of power amplifier (PA) in 60 nm GaN/Si HEMT technology. A customized transistor model enables the designing circuits operating at W-band. The all matching network of the PA was composed of equivalent transformer circuit to reduce matching loss. And then, equivalent transformer is several advantages without any additional inductive devices so that a wideband power characteristic can be achieved. The designed die area is 3900 ㎛ × 2300 ㎛. The designed results at center frequency achieved the small signal gain of 15.9 dB, the saturated output power (Psat) of 29.9 dBm, and the power added efficiency (PAE) of 24.2% at the supply voltage of 12 V.

• Journal of IKEEE
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• v.2 no.1 s.2
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• pp.1-14
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• 1998

In this paper, Antenna, LNA, Mixer, VCO, and Modulation/Demodulation in Baseband processor which are the RF main components in Wireless LAN system for ultra high-speed communications network are studied. Antenna bandwidth and selective fading due to multipath can be major obstacles in high speed digital communications. To solve this problem, wide band MSA which has loop-structure magnetic antenna characteristics is designed. Distributed mixer using dual-gate GaAs MESFET can achieve over 10dB LO/RF isolation without hybrid, and minimize circuit size. As linear mixing signal is produced, distortions can be decreased at baseband signals. Conversion gain is achieved by mixing and amplification simultaneously. Mixer is designed to have wide band characteristics using distributed amplifier. In VCO design, Oscillator design method by large signal analysis is used to produce stable signal. Modulation/Demodulation system in baseband processor, DS/SS technique which is robust against noise and interference is used to eliminate the effect of multipath propagation. DQPSK modulation technique with M-sequences for wideband PN spreading signals is adopted because of BER characteristic and high speed digital signal transmission.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2022.10a
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• pp.245-247
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• 2022

Backscattered x-ray imaging is a technology capable of acquiring an image inside an irradiated object by measuring X-rays scattered from an object. For image acquisition, the system must include an X-ray generator and a detection system for measuring scattered x-rays. The imaging device must acquire a real-time signal at sampling intervals for x-rays generated by passing through a high-speed rotating collimator, and for this purpose, a high-speed signal acquisition device is required. We developed a high-speed multi-channel signal acquisition device for converting and transmitting signals generated by the sensor unit composed of a large-area plastic scintillator and a photomultiplier tube. The developed detector is a system capable of acquiring signals at intervals of at least 15u seconds and converting and transmitting signals of up to 6 channels. And a system includes remote control functions such as high voltage, signal gain, and low level discrimination for individual calibration of each sensor. Currently, we are conducting an application test for image acquisition under various conditions.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.58-68
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• 2006

This work proposes a 10b 250MS/s $1.8mm^2$ 85mW 0.13um CMOS A/D Converter (ADC) for high-performance integrated systems such as next-generation DTV and WLAN simultaneously requiring low voltage, low power, and small area at high speed. The proposed 3-stage pipeline ADC minimizes chip area and power dissipation at the target resolution and sampling rate. The input SHA maintains 10b resolution with either gate-bootstrapped sampling switches or nominal CMOS sampling switches. The SHA and two MDACs based on a conventional 2-stage amplifier employ optimized trans-conductance ratios of two amplifier stages to achieve the required DC gain, bandwidth, and phase margin. The proposed signal insensitive 3-D fully symmetric capacitor layout reduces the device mismatch of two MDACs. The low-noise on-chip current and voltage references can choose optional off-chip voltage references. The prototype ADC is implemented in a 0.13um 1P8M CMOS process. The measured DNL and INL are within 0.24LSB and 0.35LSB while the ADC shows a maximum SNDR of 54dB and 48dB and a maximum SFDR of 67dB and 61dB at 200MS/s and 250MS/s, respectively. The ADC with an active die area of $1.8mm^2$ consumes 85mW at 250MS/s at a 1.2V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.87-93
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• 2010

This paper presents a high resolution, wide input range 2-step time-to-digital converter used in digital PLL. TDC is used to compare the DPLL output frequency with reference frequency and should be implemented with high resolution to improve the phase noise of DPLL. The conventional TDC consists of delay line realized inverters, whose resolution is determined by delay time of inverter and transistor size, resulting in limited resolution. In this paper, 2-step TDC with phase-interpolation and Time Amplifier is proposed to meet the high resolution and wide input range by implement the delay time less than an inverter delay. The gain of Time Amplifier is improved by using the delay time difference between two inverters. It is implemented in $0.13{\mu}m$ CMOS process and the die area is $800{\mu}m{\times}850{\mu}m$ Current consumption is 12 mA at the supply voltage of 1.2 V. The resolution and input range of the proposed TDC are 0.357 ps and 200 ps, respectively.

• Journal of the Korean Solar Energy Society
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• v.32 no.4
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• pp.24-33
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• 2012

Recently, finishing materials at spandrel area, a part of curtain-wall system, are gradually forced to improve thermal insulation performance in order to enhance the building energy efficiency. Also, Building Integrated Photovoltaics(BIPV) systems have been installed in the exterior side of the spandrel area, which is generally composed of windows. Those BIPVs aim to achieve high building energy efficiency and supply the electricity to building. However, if transparent BIPV module is combined with high insulated spandrel, it would reduce the PV efficiency for two major reasons. First, temperature in the air space, located between window layer and finishing layer of the spandrel area, can significantly increase by solar heat gain, because the space has a few air density relative to other spaces in building. Secondly, PV has a characteristics of decreased Voltage(Voc and Vmp) with the increased temperature on the PV cell. For these reasons, this research analyzed a direct interrelation between PV Cell temperature and electricity generation performance under different insulation conditions in the spandrel area. The different insulation conditions under consideration are 1) high insulated spandrel(HIS) 2) low insulated spandrel(LIS) 3) PV stand alone on the ground(SAG). As a result, in case of 1) HIS, PV temperature was increased and thus electricity generation efficiency was decreased more than other cases. To be specific, each cases' maximum temperature indicated that 1) HIS is $83.8^{\circ}C$, 2) LIS is $74.2^{\circ}C$, and 3) SAG is $66.3^{\circ}C$. Also, each cases yield electricity generation like that 1) HIS is 913.3kWh/kWp, 2) LIS is 942.8kWh/kWp, and 3) SAG is 981.3kWh/kWp. These result showed that it is needed for us to seek to the way how the PV Cell temperature would be decreased.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.9
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• pp.63-73
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• 2015

This work proposes a 2-channel time-interleaved (T-I) 10b 120MS/s pipeline SAR ADC minimizing offset mismatch between channels without any calibration scheme. The proposed ADC employs a 2-channel SAR and T-I topology based on a 2-step pipeline ADC with 4b and 7b in the first and second stage for high conversion rate and low power consumption. Analog circuits such as comparator and residue amplifier are shared between channels to minimize power consumption, chip area, and offset mismatch which limits the ADC linearity in the conventional T-I architecture, without any calibration scheme. The TSPC D flip-flop with a short propagation delay and a small number of transistors is used in the SAR logic instead of the conventional static D flip-flop to achieve high-speed SAR operation as well as low power consumption and chip area. Three separate reference voltage drivers for 4b SAR, 7b SAR circuits and a single residue amplifier prevent undesirable disturbance among the reference voltages due to each different switching operation and minimize gain mismatch between channels. High-frequency clocks with a controllable duty cycle are generated on chip to eliminate the need of external complicated high-frequency clocks for SAR operation. The prototype ADC in a 45nm CMOS technology demonstrates a measured DNL and INL within 0.69LSB and 0.77LSB, with a maximum SNDR and SFDR of 50.9dB and 59.7dB at 120MS/s, respectively. The proposed ADC occupies an active die area of 0.36mm2 and consumes 8.8mW at a 1.1V supply voltage.