• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.2
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• pp.106-113
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• 2006

Electrical properties of $Si_{0.88}Ge_{0.12}(C)$ p-MOSFETs have been exploited in an effort to investigate $Si_{0.88}Ge_{0.12}(C)$ channel structures designed especially to suppress diffusion of dopants during epitaxial growth and subsequent fabrication processes. The incorporation of 0.1 percent of carbon in $Si_{0.88}Ge_{0.12}$ channel layer could accomodate stress due to lattice mismatch and adjust bandgap energy slightly, but resulted in deteriorated current-voltage properties in a broad range of operation conditions with depressed gain, high subthreshold current level and many weak breakdown electric field in gateoxide. $Si_{0.88}Ge_{0.12}(C)$ channel structures with boron delta-doping represented increased conductance and feasible use of modulation doped device of $Si_{0.88}Ge_{0.12}(C)$ heterostructures.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.10
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• pp.832-835
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• 2017

In this paper, V-band differential low noise amplifier(LNA) using 65-nm CMOS process for high speed wireless data communication is presented. The LNA is composed of 3-stage common-source differential amplifiers with neutralization of feedback capacitances using MOS capacitors and impedance matching utilizing transformers. The fabricated LNA has a peak gain of 23 dB at 63 GHz and 3 dB bandwidth of 6 GHz. The chip area of LNA is $0.3mm^2$ and the LNA consumes 32 mW DC power from 1.2 V supply voltage.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.65 no.6
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• pp.1108-1114
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• 2016

The cause of failure in the AT feeding system is divided into grounding, short-circuit of feeding circuit and internal faults of the railway substation. Since the fault current is very high, real-time current is detected and the failure must be immediately removed. In this paper, a new DC offset elimination filter that can remove component to decrease in the form of exponential function using low-pass filter was proposed in order to extract the fundamental wave from distorted fault current. In order to confirm the performance of the proposed filter method, AT feeder system was modelled by simulation tool and simulations were performed under various conditions such as fault location, fault resistance and fault voltage phase angle in case of trolley-rail short-circuit fault. When applying the proposed DC-offset removal method, it can be seen that the phase delay and gain error did not appear.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.443-450
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• 2014

This paper presents a 20-Gb/s optical receiver circuit fabricated with standard 65-nm CMOS technology. Our receiver circuits are designed with consideration for parasitic inductance and capacitance due to bonding wires connecting the photodetector and the circuit realized separately. Such parasitic inductance and capacitance usually disturb the high-speed performance but, with careful circuit design, we achieve optimized wide and flat response. The receiver circuit is composed of a transimpedance amplifier (TIA) with a DC-balancing buffer, a post amplifier (PA), and an output buffer. The TIA is designed in the shunt-feedback configuration with inductive peaking. The PA is composed of a 6-stage differential amplifier having interleaved active feedback. The receiver circuit is mounted on a FR4 PCB and wire-bonded to an equivalent circuit that emulates a photodetector. The measured transimpedance gain and 3-dB bandwidth of our optical receiver circuit is 84 $dB{\Omega}$ and 12 GHz, respectively. 20-Gb/s $2^{31}-1$ electrical pseudo-random bit sequence data are successfully received with the bit-error rate less than $10^{-12}$. The receiver circuit has chip area of $0.5mm{\times}0.44mm$ and it consumes excluding the output buffer 84 mW with 1.2-V supply voltage.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.62 no.2
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• pp.232-238
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• 2013

In this paper we describe the maximum energy transfer of CSA(Capacitive Switching Antenna). CSA which is radiated antenna system contain energy storage and switch, antenna needs to high voltage source for electrical field radiation experiment. In this experiment we employed Marx generator as a charging source. CSA can radiate electrical field more efficiently by varying antenna capacitance. The electromagnetic generation system which was using CSA has some advantages which are more simple and more effective compared to exist system. We evaluated the performance of electromagnetic wave generating system using CSA. As a result UWB gain of system is 0.47, It is higher level than exist system is 0.3. Radiated electrical field strength at 1m is 70kV/m. It is measured by D-dot sensor and gap distance is 20mm. Center frequency of CSA is approximately 25MHz. When vary the antenna gap distance from 50mm to 20mm, we can find the radiation field strength is decrease and antenna center frequency is increased. We also simulated the energy transfer efficiency to compare with experiment result. Consequentially, CSA needs to appropriate capacitance which is similar value from marx generator for maximum energy transfer, and gap is less than 1mm to increase the CSA capacitance.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.53 no.3
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• pp.122-128
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• 2004

This paper presents a control approach for designing a fuzzy-PI controller for a synchronous generator excitation and SVC system. A combination of thyristor-controlled reactors and fixed capacitors(TCR-FC) type SVC is recognized as having the most flexible control and high speed response, which has been widely utilized in power systems, is considered and designed to improve the response of a synchronous generator, as well as controlling the system voltage. A Fuzzy-PI controller for SVC system was proposed in this paper. The PI gain parameters of the proposed Fuzzy-PI controller which is a special type of PI ones are self-tuned by fuzzy inference technique. It is natural that the fuzzy inference technique should be based on humans intuitions and empirical knowledge. Nonetheless, the conventional ones were not so. Therefore, In this paper, the fuzzy inference technique of PI gains using MMGM(Min Max Gravity Method) which is very similar to humans inference procedures, was presented and applied to the SVC system. The system dynamic responses are examined after applying all small disturbance condition.

• Journal of IKEEE
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• v.25 no.1
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• pp.133-138
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• 2021

We propose a Ku-band three-stack CMOS power amplifier to enhance the output power and efficiency. To minimize the dc power consumption, the driver stage is designed using common-source structure. To obtain high output power and utilize a voltage combining method, the power stage is designed using stack structure. To verify the proposed power amplifier structure, we design a Ku-band power amplifier using 65-nm RFCMOS process which provide nine metal layers. The P1dB, power-added efficiency, and gain are higher than 20 dBm, 23 dB, and 25%, respectively, while the operating frequency is 14 GHz-16 GHz.

• Journal of IKEEE
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• v.27 no.1
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• pp.109-115
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• 2023

In this paper, we design and implement an Ultra-Wide Band (UWB, 3.1~10.6 GHz) antenna with 5G mobile communication (3.42~3.70 GHz) and Wireless Local Area Network (WLAN, 5.15~5.825 GHz) bands rejection characteristics. The proposed antenna consists of a planar radiation patch with two slots. The upper slot contributes to reject 5G mobile communication band and the lower slot contributes to reject WLAN band. The Voltage Standing Wave Ratio (VSWR) values of the proposed antenna show good performances in whole UWB band except for rejection bands based on VSWR 2.0. The proposed UWB antenna was simulated using High Frequency Struture Simulator (HFSS) by Ansoft. The simulated antenna showed dual rejection bands of 3.31~3.92 GHz and 5.04~5.90 GHz in UWB band, and measured antenna showed dual rejection bands of 3.35~3.97 GHz and 5.06~5.97 GHz. The largest VSWR values measured at each rejection band are 13.60 at 3.64 GHz and 10.25 at 5.52 GHz. The measured maximum gain is 5.31 dBi at 10.00 GHz. The lowest gains for the measured antenna at rejection bands are -8.73 dBi at 3.70 GHz and -4.36 dBi at 5.56 GHz.

• ETRI Journal
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• v.45 no.6
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• pp.996-1006
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• 2023

Renewable energy is promoted massively to overcome problems that fossil fuel power plants generate. One popular renewable energy type that offers easy installation is a photovoltaic (PV) system. However, the energy harvested through a PV system is not optimal because influenced by exposure to solar irradiance in the PV module, which is constantly changing caused by weather. The maximum power point tracking (MPPT) technique was developed to maximize the energy potential harvested from the PV system. This paper presents the MPPT technique, which is operated on a new high-gain voltage DC/DC converter that has never been tested before for the MPPT technique in PV systems. Fuzzy logic (FL) was used to operate the MPPT technique on the converter. Conventional and adaptive perturb and observe (P&O) techniques based on variables step size were also used to operate the MPPT. The performance generated by the FL algorithm outperformed conventional and variable step-size P&O. It is evident that the oscillation caused by the FL algorithm is more petite than variables step-size and conventional P&O. Furthermore, FL's tracking speed algorithm for tracking MPP is twice as fast as conventional P&O.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.122-130
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• 2013

This work proposes a 12b 100MS/s 45nm CMOS four-step pipeline ADC for high-speed digital communication systems requiring high resolution, low power, and small size. The input SHA employs a gate-bootstrapping circuit to sample wide-band input signals with an accuracy of 12 bits or more. The input SHA and MDACs adopt two-stage op-amps with a gain-boosting technique to achieve the required DC gain and high signal swing range. In addition, cascode and Miller frequency-compensation techniques are selectively used for wide bandwidth and stable signal settling. The cascode current mirror minimizes current mismatch by channel length modulation and supply variation. The finger width of current mirrors and amplifiers is laid out in the same size to reduce device mismatch. The proposed supply- and temperature-insensitive current and voltage references are implemented on chip with optional off-chip reference voltages for various system applications. The prototype ADC in a 45nm CMOS demonstrates the measured DNL and INL within 0.88LSB and 1.46LSB, respectively. The ADC shows a maximum SNDR of 61.0dB and a maximum SFDR of 74.9dB at 100MS/s, respectively. The ADC with an active die area of $0.43mm^2$ consumes 29.8mW at 100MS/s and a 1.1V supply.