• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.7
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• pp.1386-1392
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• 2009

An analysis is presented for super-high-speed optical demodulation by an avalanche photodiode(APD) with electric mixing. A normalized gain is defined to evaluate the performance of the optical mixing detection. Unlike previous work, we include the effect of the nonlinear variation of the APD capacitance with bias voltage as well as the effect of parasitic and amplifier input capacitance. As a results, the normalized gain is dependent on the signal frequency and the frequency difference between the signal and the local oscillator frequency. However, the current through the equivalent resistance of the APD is almost independent of signal frequency. The mixing output is mainly attributed to the nonlinearity of the multiplication factor. We show also that there is an optimal local oscillator voltage at which the normalized gain is maximized for a given avalanche photodiode.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.983-986
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• 2003

This paper describes a 2.5V 80dB 360MHz CMOS VGA. A new variable degeneration resistor is proposed where the dc voltage drop over the degeneration resistor is minimized and employed in designing a low-voltage and high-speed CMOS VGA. HSPICE simulation results using a 0.25${\mu}{\textrm}{m}$ CMOS process parameters show that the designed VGA provides a 3dB bandwidth of 360MHz and a 80dB gain control range in 2dB step. Gain errors are less than 0.4dB at 200MHz and less than 1.4dB at 300MHz. The designed circuit consumes 10.8mA from a 2.5V supply and its die area is 1190${\mu}{\textrm}{m}$$\times$360${\mu}{\textrm}{m}$.

• The Transactions of the Korean Institute of Power Electronics
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• v.23 no.2
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• pp.121-128
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• 2018

This work proposes a simple control method of a buck-type active power decoupling circuit that can minimize the ripple values in the dc link voltage. The proposed method utilizes a simplified duty calculation method and an optimal compensation gain tracking algorithm with variable-step approach. Thus, the dc link voltage ripple can be effectively reduced through the proposed method along with rapid response in tracking the optimum compensation gain. Moreover, the proposed method has better dynamic responses in the load fluctuation or abnormal situation. MATLAB/Simulink simulation and hardware-in-the-loop-simulation(HILS)-based experimental results are presented to validate the effectiveness of the proposed control method.

• Journal of IKEEE
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• v.23 no.3
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• pp.1054-1060
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• 2019

A extension of the high boost voltage-lift DC-DC converter with large conversion ratio has been proposed in this paper. The proposed extension is combined the switched-inductor cell (SL-cell) and modular voltage cell (MV-cell). The proposed structure can achieve the large voltage conversion without high duty-cycle and the low voltage of the components. Moreover, the PID controller for novel SL-MV voltage-lift DC-DC converter also introduces. This technique a good-performance output voltage can kept constant with an good transient performance when the output load is suddenly changed. In order to prove the theoretical analysis, the experimental setup has been built for the DC load of $150[{\Omega}]$ and $300[{\Omega}]$. In addition, the transient of output voltage has been tested to determine the controller. Experimental results validate the effectiveness of the theoretical analysis proving the satisfactory converter performance.

• ETRI Journal
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• v.42 no.6
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• pp.943-950
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• 2020

We propose 8.2-GHz band radar RFICs for an 8 × 8 phased-array frequency-modulated continuous-wave receiver developed using 65-nm CMOS technology. This receiver panel is constructed using a multichip solution comprising fabricated 2 × 2 low-noise amplifier phase-shifter (LNA-PS) chips and a 4ch RX front-end chip. The LNA-PS chip has a novel phase-shifter circuit for low-voltage operation, novel active single-to-differential/differential-to-single circuits, and a current-mode combiner to utilize a small area. The LNA-PS chip shows a power gain range of 5 dB to 20 dB per channel with gain control and a single-channel NF of 6.4 dB at maximum gain. The measured result of the chip shows 6-bit phase states with a 0.35° RMS phase error. The input P1 dB of the chip is approximately -27.5 dBm at high gain and is enough to cover the highest input power from the TX-to-RX leakage in the radar system. The gain range of the 4ch RX front-end chip is 9 dB to 30 dB per channel. The LNA-PS chip consumes 82 mA, and the 4ch RX front-end chip consumes 97 mA from a 1.2 V supply voltage. The chip sizes of the 2 × 2 LNA-PS and the 4ch RX front end are 2.39 mm × 1.3 mm and 2.42 mm × 1.62 mm, respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.6
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• pp.818-823
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• 2014

A high-gain wideband low noise amplifier (LNA) using $0.25-{\mu}m$ Gallium-Nitride (GaN) MMIC technology is presented. The LNA shows 8 GHz to 15 GHz operation by a distributed amplifier architecture and high gain with an additional common source amplifier as a mid-stage. The measurement results show a flat gain of $25.1{\pm}0.8dB$ and input and output matching of -12 dB for all targeted frequencies. The measured minimum noise figure is 2.8 dB at 12.6 GHz and below 3.6 dB across all frequencies. It consumes 98 mA with a 10-V supply. By adjusting the gate voltage of the mid-stage common source amplifier, the overall gain is controlled stably from 13 dB to 24 dB with no significant variations of the input and output matching.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.9
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• pp.54-61
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• 2016

A 6-Gbps single-ended receiver with a linear equalizer and a self-reference generator is proposed for a high-speed interface with the double data rate. The proposed single-ended receiver uses a common gate amplifier to increase a voltage gain for an input signal with low voltage level. The continuous-time linear equalizer which reduces gain to the low frequencies and achieves high-frequency peaking gain is implemented in the common gate amplifier. Furthermore, a self-reference generator, which is controlled with the resolution 2.1 mV using digital averaging method, is implemented to maximize the voltage margin by removing the offset noise of the common gate amplifier. The proposed single-ended receiver is designed using a 65-nm CMOS process with 1.2-V supply and consumes the power of 15 mW at the data rate of 6 Gbps. The peaking gain in the frequency of 3 GHz of the designed equalizer is more than 5 dB compared to that in the low frequency.

• Journal of Electrical Engineering and Technology
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• v.12 no.3
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• pp.1187-1194
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• 2017

In this paper, a high step-up DC-DC PWM converter with continuous input current and low voltage stress is presented for renewable energy application. The proposed converter is composed of a boost converter integrated with an auxiliary step-up circuit. The auxiliary circuit uses an additional coupled inductor and a balancing capacitor with voltage doubler and switching capacitor technique to achieve high step-up voltage gain with an appropriate switch duty cycle. The switched capacitors are charged in parallel and discharged in series by the coupled inductor, stacking on the output capacitor. In the proposed converter, the voltage stress on the main switch is clamped, so a low voltage switch with low ON resistance can be used to reduce the conduction loss which results in the efficiency improvement. A detailed discussion on the operating principle and steady-state analyses are presented in the paper. To justify the theoretical analysis, experimental results of a 200W 40/400V prototype is presented. In addition, the conducted electromagnetic emissions are measured which shows a good EMC performance.

• ETRI Journal
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• v.30 no.5
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• pp.729-734
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• 2008

Wireless communication systems, such as WLAN or Bluetooth receivers, employ preamble data to estimate the channel characteristics, introducing stringent settling-time constraints. This makes the use of traditional closed-loop feedback automatic gain control (AGC) circuits impractical for these applications. In this paper, a compact feedforward AGC circuit is proposed to obtain a fast-settling response. The AGC has been implemented in a 0.35 ${\mu}m$ standard CMOS technology. Supplied at 1.8 V, it operates with a power consumption of 1.6 mW at frequencies as high as 100 MHz, while its gain ranges from 0 dB to 21 dB in 3 dB steps through a digital word. The settling time of the circuit is below 0.25 ${\mu}s$.

• Journal of Electrical Engineering and Technology
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• v.12 no.3
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• pp.1082-1089
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• 2017

Negative output elementary super lift Luo converter (NOESLLC), which has the significant advantages including high-voltage transfer gain, high efficiency, high power density, and reduced output voltage/inductor current ripples when compared to the traditional DC-DC converters, is an attractive DC-DC converter for the field of negative DC voltage applications. In this study, in consideration of the voltage across the energy transferring capacitor changing abruptly at the beginning of each switching cycle, the improved averaged model of the NOESLLC operating in continuous conduction mode (CCM) is established. The improved DC model and transfer functions of the system are derived and analyzed. The current mode control is applied for this NOESLLC. The results from the theoretical calculations, the PSIM simulations and the circuit experiments show that the improved DC model and transfer functions here are more effective than the existed ones of the NOESLLC to describe its real dynamical behaviors.