• Title/Summary/Keyword: High leakage current

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Characteristics of Amorphous/Polycrystalline $BaTiO_3$ Double Layer Thin Films with High Performance Prepared New Stacking Method and its Application to AC TFEL Device (새로운 적층방법으로 제조된 고품위 비정질/다결정 $BaTiO_3$ 적층박막의 특성과 교류 구동형 박막 전기 발광소자에의 응용)

  • 송만호;이윤희;한택상;오명환;윤기현
    • Journal of the Korean Ceramic Society
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    • v.32 no.7
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    • pp.761-768
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    • 1995
  • Double layered BaTiO3 thin films with high dielectric constant as well as good insulating property were prepared for the application to low voltage driving thin film electroluminescent (TFEL) device. BaTiO3 thin films were formed by rf-magnetron sputtering technique. Amorphous and polycrystalline BaTiO3 thin films were deposited at the substrate temperatures of room temperature and 55$0^{\circ}C$, respectively. Two kinds of films prepared under these conditions showed high resistivity and high dielectric constant. The figure of merit (=$\varepsilon$r$\times$Eb.d) of polycrystalline BaTiO3 thin film was very high (8.43$\mu$C/$\textrm{cm}^2$). The polycrystalline BaTiO3 showed a substantial amount of leakage current (I), under the high electric field above 0.5 MV/cm. The double layered BaTiO3 thin film, i.e., amorphous BaTiO3 layer coated polycrystalline BaTiO3 thin film, was prepared by the new stacking method and showed very good dielectric and insulating properties. It showed a high dielectric constant fo 95 and leakage current density of 25 nA/$\textrm{cm}^2$ (0.3MV/cm) with the figure of merit of 20$\mu$C/$\textrm{cm}^2$. The leakage current density in the double layered BaTiO3 was much smaller than that in polycrystalline BaTiO3 under the high electric field. The saturated brightness of the devices using double layered BaTiO3 was about 220cd/$m^2$. Threshold voltage of TFEL devices fabricated on double layered BaTiO3 decreased by 50V compared to the EL devices fabricated on amorphous BaTiO3.

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High Frequency Model of Inverter-fed Induction Motor (인버터 구동 유도 전동기 고주파 모델링)

  • Hong, Sun-Ki
    • Proceedings of the KIEE Conference
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    • 2001.07b
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    • pp.795-797
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    • 2001
  • Voltage varing Fate dv/dt which is applied to induction motor usually makes unnegligible leakage current and it flows through stator winding and motor frame. This kind of harmonic leakage current makes effect on power source and cuases electromagnetic trouble because the motor frame has earth. Therefore in this study, a high frequency induction motor model is developed and analyze the motor performance to explain the phenomena. Inverter model is also developed and is combined with the motel model to prepare the basis of the high frequency effects on inverter fed induction motor.

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Variations of Interface Potential Barrier Height and Leakage Current of (Ba, Sr)$TiO_3$ Thin Films Deposited by Sputtering Process

  • Hwang, Cheol-Seong;Lee, Byoung-Taek
    • The Korean Journal of Ceramics
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    • v.2 no.2
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    • pp.95-101
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    • 1996
  • Variations of the leakage current behaviors and interface potential barrier $({\Phi}_B)$ of rf-sputter deposited (Ba, Sr)$TiO_3$ (BST) thin films with thicknesses ranging from 20 nm to 150nm are investigated as a function of the thickness and bias voltages. The top and bottom electrodes are dc-sputter-deposited Pt films. ${\Phi}_B$ critically depends on the BST film deposition temperature, postannealing atmosphere and time after the annealing. The postannealing under $N_2$ atmosphere results in a high interface potential barrier height and low leakage current. Maintaining the BST capacitor in air for a long time reduces the ${\Phi}_B$ from about 2.4 eV to 1.6 eV due to the oxidation. ${\Phi}_B$ is not so dependent on the film thickness in this experimental range. The leakage conduction mechanism is very dependent on the BST film thickness; the 20 nm thick film shows tunneling current, 30 and 40 nm thick films show Shottky emission current.

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A Study on the microstructure and Surge Characteristics of ZnO varistors for distribution Arrester (배전급 피뢰기용 ZnO 바리스터 소자의 미세구조 및 서지 특성에 관한 연구)

  • 김석수;조한구;박태곤;박춘현;정세영;김병규
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.15 no.2
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    • pp.190-197
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    • 2002
  • In this thesis, ZnO varistors with various formulation, such as A∼E, were fabricated according to ceramic fabrication method. The microstructure, electrical properties, and surge characteristics of ZnO varistors were investigated according to ZnO varistors with various formulation. In the microstructure, A∼E\`s ZnO varistor ceramics sintered at 1130$\^{C}$ was consisted of ZnO grain(ZnO), spinel phase (Zn$\_$2.33/Sb$\_$0.67/O$\_$4/), Bi-rich phase(Bi$_2$O$_3$) and intergranuler phase, wholly. Lightning impulse residual voltage of A, B, C and E\`s ZnO varistors suited standard characteristics, below 12kV at current of 5kA. On the contrary, D\`s ZnO varistor exhibited high residual voltage as high reference voltage. In the accelerated aging test, leakage current and watt loss of B, C and D\`s ZnO varistors increases abruptly with stress time under the first a.c. stress(115$\^{C}$/3.213kV/300h). Consequently, C varistor exhibited a thermal run away. On the contrary, leakage current and watt loss of A and C\`s ZnO varistors which show low initial leakage current exhibited constant characteristics. After high current impulse test, A\`s ZnO varistor has broken the side of varistor but impulse current flowed. On the contrary, E\`s ZnO Varistor exhibited good discharge characteristics which the appearance of varistor was not wrong such as puncture, flashover, creaking and other significant damage. After long duration impulse current test, E\`s ZnO varistor exhibited good discharge characteristics which the appearance of varistor was not wrong such as puncture, flashover, creaking and other significant damage. After high current impulse test and long duration impulse current test, E\`s ZnO varistor exhibited very good characteristics which variation rate of residual voltage is 1.4% before and after test.

Self-timed Current-mode Logic Family having Low-leakage Current for Low-power SoCs (저 전력 SoC를 위한 저 누설전류 특성을 갖는 Self-Timed Current-Mode Logic Family)

  • Song, Jin-Seok;Kong, Jeong-Taek;Kong, Bai-Sun
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.8
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    • pp.37-43
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    • 2008
  • This paper introduces a high-speed low-power self-timed current-mode logic (STCML) that reduces both dynamic and leakage power dissipation. STCML significantly reduces the leakage portion of the power consumption using a pulse-mode control for shorting the virtual ground node. The proposed logic style also minimizes the dynamic portion of the power consumption due to short-circuit current by employing an enhanced self-timing buffer. Comparison results using a 80-nm CMOS technology show that STCML achieves 26 times reduction on leakage power consumption and 27% reduction on dynamic power consumption as compared to the conventional current-mode logic. They also indicate that up to 59% reduction on leakage power consumption compared to differential cascode voltage switch logic (DCVS).

Stress Induced Leakage Currents in the Silicon Oxide Insulator with the Nano Structures (나노 구조에서 실리콘 산화 절연막의 스트레스 유기 누설전류)

  • 강창수
    • Journal of the Institute of Electronics Engineers of Korea TE
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    • v.39 no.4
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    • pp.335-340
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    • 2002
  • In this paper, the stress induced leakage currents of thin silicon oxides is investigated in the ULSI implementation with nano structure transistors. The stress and transient currents associated with the on and off time of applied voltage were used to measure the distribution of high voltage stress induced traps in thin silicon oxide films. The stress and transient currents were due to the charging and discharging of traps generated by high stress voltage in the silicon oxides. The transient current was caused by the tunnel charging and discharging of the stress generated traps nearby two interfaces. The stress induced leakage current will affect data retention in electrically erasable programmable read only memories. The oxide current for the thickness dependence of stress current, transient current, and stress induced leakage currents has been measured in oxides with thicknesses between 113.4${\AA}$ and 814${\AA}$, which have the gate area $10^3cm^2$. The stress induced leakage currents will affect data retention and the stress current, transient current is used to estimate to fundamental limitations on oxide thicknesses.

Prediction of Flashover and Pollution Severity of High Voltage Transmission Line Insulators Using Wavelet Transform and Fuzzy C-Means Approach

  • Narayanan, V. Jayaprakash;Sivakumar, M.;Karpagavani, K.;Chandrasekar, S.
    • Journal of Electrical Engineering and Technology
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    • v.9 no.5
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    • pp.1677-1685
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    • 2014
  • Major problem in the high voltage power transmission line is the flashover due to polluted ceramic insulators which leads to failure of equipments, catastrophic fires and power outages. This paper deals with the development of a better diagnostic tool to predict the flashover and pollution severity of power transmission line insulators based on the wavelet transform and fuzzy c-means clustering approach. In this work, laboratory experiments were carried out on power transmission line porcelain insulators under AC voltages at different pollution conditions and corresponding leakage current patterns were measured. Discrete wavelet transform technique is employed to extract important features of leakage current signals. Variation of leakage current magnitude and distortion ratio at different pollution levels were analyzed. Fuzzy c-means algorithm is used to cluster the extracted features of the leakage current data. Test results clearly show that the flashover and pollution severity of power transmission line insulators can be effectively realized through fuzzy clustering technique and it will be useful to carry out preventive maintenance work.

Improvement of Structure to Prevent Water Infiltration and oil leakage for Reduction Units of KTX (KTX 감속구동장치 수분유입 및 누유 방지를 위한 구조개선)

  • Lee, Min-Soo;Kim, Yong-Kee
    • Proceedings of the KSR Conference
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    • 2007.05a
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    • pp.20-25
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    • 2007
  • KTX is being operated on Kyung-Pu High Speed Railroad Line and Ho-Nam Railroad Line from April 2004. Reduction units is occurring water infiltration at heavy snow and oil leakage because of labyrinth structure. This paper describes design method and evaluation technology to improve structure to prevent water infiltration and oil leakage for reduction units of KTX. This reduction units need high power and high speed to run and they have to make optimal lubricant without change current interface.

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A Study on Modeling of High-Frequency Leakage Currents in PWM Inverter Feeding an Induction Motor (유도전동기의 PWM제어와 누설 축전류 발생 모델링에 관한 연구)

  • 이재호;임경내;전진휘;박성준;김철우
    • Proceedings of the KIPE Conference
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    • 1998.07a
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    • pp.221-224
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    • 1998
  • A PWM inverter with an induction motor often has a problem with a high-frequency leakage current that flows through the distributed electrostatic capacitance from the motor windings to ground. This paper presents an equivalent circuit for high-frequency leakage currents in PWM inverter feeding an induction motor, which forms an LCR series resonant circuit.

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Dielectric properties with heat-input condition of PZT thin films for ULSI's capacitor -1- A study on the improvement of leakage current of PZT thin films using a amorphous PZT layer (초고집적회로의 커패시터용 PZT박막의 입열 조건에 따른 유전특성 -1- 비정질 PZT를 사용한 PZT 박막의 누설전류 개선에 관한 연구)

  • 마재평;백수현;황유상
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.32A no.12
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    • pp.101-107
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    • 1995
  • To improve the leakage current, we developed two step sputtering method where PZT thin film in first deposited at room temperature followed by 600.deg. C deposition. The method used an amorphous PZT layer deposited at room temperature to keep a stable interface during sputtering at high temperature. PZT thin films were deposited on Pt/Ti/SiO$_{2}$/Si substrate at room temperature and 600.deg. C sequentially. The effect of the layer deposited at room temperature was investigated with regard to I-V characteristics and P-E hysteresis loop. In the case of the sample with the layer deposited at room temperature, both leakage current and dielectric constant were decreased. The thicker the layer deposited at room temperature was, the lower dielectric constant was. However, leakage current was indepenent of the variation of the thickness ratio. The sample with 200$\AA$ of the layer deposited at room temperature showed the most promising results in both dielectric constant and leakage current.

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