• ETRI Journal
• /
• v.29 no.4
• /
• pp.536-538
• /
• 2007

We propose and describe the fabrication of a linear power amplifier (LPA) using a new analog feedforward method for the IMT-2000 frequency band (2,110-2,170 MHz). The proposed analog feedforward circuit, which operates without a pilot tone or a microprocessor, is a small and simple structure. When the output power of the fabricated LPA is about 44 dBm for a two-tone input signal in the IMT-2000 frequency band, the magnitude of the intermodulation signals is below -60 dBc and the power efficiency is about 7%. In comparison to the fabricated main amplifier, the magnitude of the third intermodulation signal decreases over 24 dB in the IMT-2000 frequency band.

• Journal of electromagnetic engineering and science
• /
• v.16 no.3
• /
• pp.143-149
• /
• 2016

This work presents a method used for designing a broadband class-E power amplifier that combines the two techniques of a nonlinear shunt capacitance and a low quality factor of a series resonator. The nonlinear shunt capacitance theory accurately extracts the value of class-E components. In addition, the quality factor of the series resonator was considered to obtain a wide bandwidth for the power amplifiers. The purpose of using this method was to produce a simple topology and a high efficiency, which are two outstanding features of a class-E power amplifier. The experimental results show that a design was created using from a 130 to 180 MHz frequency with a bandwidth of 32% and a peak measured power added efficiency of 84.8%. This prototype uses an MRF282SR1 MOSFET transistor at a 3-W output power level. Furthermore, a summary of the experimental results compared with other high-efficiency articles is provided to validate the advantages of this method.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.36C no.5
• /
• pp.57-66
• /
• 1999

This paper describes a 12b, 50 Msample/s CMOS AID converter using an acquisition-time minimization technique for the high-speed sampling rate of 50 MHz level. The proposed ADC is implemented in a $0.35\mu\textrm{m}$ double-poly five-metal n-well CMOS technology and adopts a typical multi-step pipelined architecture to optimize sampling rate, resolution, and chip area. The speed limitation of conventional pipelined ADCs comes from the finite bandwidth and resulting speed of residue amplifiers. The proposed acquisition-time minimization technique reduces the acquisition time of residue amplifiers and makes the waveform of amplifier outputs smooth by controlling the operating current of residue amplifiers. The simulated power consumption of the proposed ADC is 197 mW at 3 V with a 50 MHz sampling rate. The chip size including pads is $3.2mm\times3.6mm$.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.19 no.1
• /
• pp.231-238
• /
• 2019

In this paper, we have studied how to improve the amplifiers efficiency by minimizing the combining loss when several unit power amplifiers are combined to obtain high output power. Specifically, we have developed Ka-band Spatial Combining Amplifier. The fabricated Spatial Combining Amplifier is a Ka-band 20W class SSPA, which uses a 5W class unit amplifier module 8EA designed using a GaN bare die. We also combined The unit amplifier module using 8-way spatial divider and combiner with a hybrid radial structure. The output combining loss of the fabricated spatial coupler is about 0.334dB, which is about 92.6% efficiency. In this paper, we developed a Spatial Combining Amplifier with a maximum saturation output of 10W and a power addition efficiency of over 15%. As a result, we achieved the maximum saturation output of 30W and the power addition efficiency of 19%.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.6 no.4
• /
• pp.275-280
• /
• 2006

We propose Doherty power amplifier structure which can be integrated in Silicon RF ICs. Doherty power amplifiers are widely used in RF transmitters, because of their high Power Added Efficiency (PAE) and good linearity. In this paper, it is proposed that a method to replace the quarter wavelength coupler with IQ up-conversion mixers to achieve 90 degree phase shift, which allows on-chip Doherty amplifier. This idea is implemented and manufactured in CMOS 5 GHz band direct-conversion RF transmitter. We measured a 3dB improvement output RF power and linearity.

• Journal of electromagnetic engineering and science
• /
• v.16 no.1
• /
• pp.52-56
• /
• 2016

This paper suggests a class-F power amplifier with split open-end stubs to provide a broadband high-efficiency operation. These stubs are designed to have wide bandwidth by splitting wide open-end stubs into narrower stubs connected in shunt in an output matching network for class-F operation. In contrast to conventional wideband class-F designs, which theoretically need a large number of matching lines, this method requires fewer transmission lines, resulting in a compact circuit implementation. In addition, the open-end stubs are designed with slant ends to achieve additional wide bandwidth. To verify the suggested design, a 10-W class-F power amplifier operating at 1.7 GHz was implemented using a commercial GaN transistor. The measurement results showed a peak drain efficiency of 82.1% and 750 MHz of bandwidth for an efficiency higher than 63%. Additionally, the maximum output power was 14.45 W at 1.7 GHz.

• ETRI Journal
• /
• v.35 no.2
• /
• pp.226-233
• /
• 2013

This paper presents a two-stage power-efficient class-AB operational transconductance amplifier (OTA) based on an adaptive biasing circuit suited to low-power dissipation and low-voltage operation. The OTA shows significant improvements in driving capability and power dissipation owing to the novel adaptive biasing circuit. The OTA dissipates only $0.4{\mu}W$ from a supply voltage of ${\pm}0.6V$ and exhibits excellent high driving, which results in a slew rate improvement of more than 250 times that of the conventional class-AB amplifier. The design is fabricated using $0.18-{\mu}m$ CMOS technology.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.9 no.2
• /
• pp.295-300
• /
• 2005

In this paper we have designed a two-stage Class I power amplifier operated at 2.4CHz for Class-1 Bluetooth application. The power amplifier employs class-I topology to exploit its soft-switching property for high efficiency. The latch-structured pre-amplifier with amplifiers makes its output signal as sharp as possible for soft switching of the next power amplifier. It improves the overall efficiency of the proposed power amplifier. It shows 65.8$\%$ PAE, 20dB power gain and 20dBm output power.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.17 no.11 s.114
• /
• pp.1030-1039
• /
• 2006

A high power and high gain Doherty amplifier is designed by using embedded driver amplifiers in the final stage. The operational characteristics of a two-stage Doherty amplifier are analyzed, as a function of the two-stage peaking amplifier gate biases. The driver stages and final output stages are implemented using two single-ended MRF21045s and a single push-pull packaged MRF5P21180, respectively. This two-stage Doherty amplifier demonstrated 27 dB gain with a PAE of 23 % at 15 W average output power.

• Proceedings of the IEEK Conference
• /
• 2000.11a
• /
• pp.321-324
• /
• 2000

본 논문은 전력증폭기 정합회로 설계시 주어진 임피던스를 가지고 Ansoft사의 Ensemble을 이용해 기본적인 정합회로를 설계하였다. MHL21336 , MRF21030 ,MRF21125로 대전력 증폭기를 설계 및 제작하여 측정해본 결과 전체 이득이 52㏈, 대역폭 안에서 이득 평탄도는 ±0.37㏈ 정도, 출력이 PEP 5l㏈m에서 -30㏈c의 결과를 얻었다. Bias 전류에 대한 5㎒ Tone-space IMD 특성곡선을 측정해 본 결과 기지국용 대전력 증폭기로 사용할 수 있음을 보였다.