• 대한전자공학회논문지TC
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• 제49권4호
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• pp.9-17
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• 2012

이 논문에서는 광대역 신호에 대한 전력 증폭기의 메모리 효과를 보이고, 메모리 효과와 결합된 비선형성의 보상 방법을 제시하고 그 성능을 분석한다. 메모리 효과와 결합된 전력 증폭기의 모델링과 보상을 위해 볼테라 급수 모델, 위너 모델, 그리고 해머스타인 모델을 검토하였다. 보상 방법으로는 디지털 피드포워드 기술을 제안하였다. 이 방식은 아날로그 방식의 피드포워드 방식에 비해 안정성과 환경 적응성 등이 우수하고, 기존의 디지털 비선형 보상 방식들에 비해 구조가 간단하다. 애질런트사의 ADS를 이용한 모의실험을 통하여 성능을 살펴본 결과 주파수대역 재성장이 20 dB 이상 억압되었으며, 최소한 10 dB 정도의 백-오프 효과가 있음을 확인하였다. 보상 성능, 구현의 복잡도, 수렴 속도 등을 고려할 때 위너 모델이 제안하는 방식에 가장 적합하다는 결론을 내릴 수 있다.

• 한국전자파학회논문지
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• 제25권1호
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• pp.53-61
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• 2014

본 논문에서는 고조파 정합 기법을 이용하여 고효율 GaN HEMT 전력 증폭기를 설계 및 제작하고, 그 특성을 측정하였다. 고효율 특성을 얻기 위해 고조파 로드풀 시뮬레이션을 활용하였다. 즉, 기본 주파수뿐만 아니라 2차, 3차 등의 고조파에서 최적의 부하 임피던스를 찾아내었다. 이러한 고조파 로드풀 시뮬레이션 결과를 바탕으로 출력 정합 회로를 설계하였다. 제작한 전력 증폭기는 중심 주파수 1.85 GHz에서 선형 전력 이득 20 dB 및 33.7 dBm의 $P_{1dB}$(1 dB gain compression point) 특성을 보였다. 그리고, 출력 전력 38.6 dBm에서 80.9 %의 최대 전력 부가 효율(Power Added Efficiency: PAE)을 나타냈으며, 이는 기존에 설계된 고효율 전력 증폭기와 비교했을 때 아주 우수한 효율 특성이다. 또한, W-CDMA 신호입력에 대한 측정 결과, 28.4 dBm의 평균 출력 전력에서 27.8 %의 PAE와 5 MHz offset 주파수에서 -38.8 dBc의 ACLR (Adjacent Channel Leakage Ratio)을 보였다. 그리고, 다항식 맞춤 방식의 디지털 전치 왜곡(Digital Predistortion: DPD) 선형화 알고리듬을 구현하여 제작된 전력 증폭기의 ACLR을 6.2 dB 정도 향상시킬 수 있었다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권1호
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• pp.28-35
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• 2007

This paper presents a high-speed flash analog-to-digital converter (ADC) for ultra wide band (UWB) receivers. In this flash ADC, the interpolating technique is adopted to reduce the number of the amplifiers and a linear and wide-bandwidth interpolating amplifier is presented. For this ADC, the transistor size for the cascaded stages is inversely scaled to improve the trade-off in bandwidth and power consumption. The active inductor peaking technique is also employed in the pre-amplifiers of comparators and the track-and-hold circuit to enhance the bandwidth. Furthermore, a digital-to-analog converter (DAC) is embedded for the sake of measurements. This chip has been fabricated in $0.13{\mu}m$ 1P8M CMOS process and the total power consumption is 113mW with 1V supply voltage. The ADC achieves 4-bit effective number of bits (ENOB) for input signal of 200MHz at 5-GSample/sec.

• Current Optics and Photonics
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• 제3권2호
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• pp.105-110
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• 2019

The visible-light communication (VLC) system is a promising candidate to fulfill the present and future demands for a high-speed, cost-effective, and larger-bandwidth communication system. VLC modulates the visible-light signals from solid-state LEDs to transmit data between transmitter and receiver, but the broadcasting and the line-of-sight propagation nature of visible-light signals make VLC a communication system with a limited operating range. We present a novel architecture to increase the operating range of VLC. In our proposed architecture, we guide the visible-light signals through the fiber and amplify the dissipated signals using visible-light fiber amplifiers (VLFAs), which are the most important and the novel devices needed for the proposed architecture of the VLC. Therefore, we design, analyze, and apply a VLFA to VLC, to overcome the inherent drawbacks of VLC. Numerical results show that under given constant conditions, the VLFA can amplify the signal up to 35.0 dB. We have analyzed the effects of fiber length, active ion concentration, pump power, and input signal power on the gain and the noise figure (NF).

• Journal of Power Electronics
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• 제15권6호
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• pp.1673-1681
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• 2015

A low dropout (LDO) regulator with a wide-bandwidth is proposed in this paper. The regulator features a Human Body Model (HBM) 8kV-class high robustness ElectroStatic Discharge (ESD) protection circuit, and two error amplifiers (one with low gain and wide bandwidth, and the other with high gain and narrow bandwidth). The dual error amplifiers are located within the feedback loop of the LDO regulator, and they selectively amplify the signal according to its ripples. The proposed LDO regulator is more efficient in its regulation process because of its selective amplification according to frequency and bandwidth. Furthermore, the proposed regulator has the same gain as a conventional LDO at 62 dB with a 130 kHz-wide bandwidth, which is approximately 3.5 times that of a conventional LDO. The proposed device presents a fast response with improved load and line regulation characteristics. In addition, to prevent an increase in the area of the circuit, a body-driven fabrication technique was used for the error amplifier and the pass transistor. The proposed LDO regulator has an input voltage range of 2.5 V to 4.5 V, and it provides a load current of 100 mA in an output voltage range of 1.2 V to 4.1 V. In addition, to prevent damage in the Integrated Circuit (IC) as a result of static electricity, the reliability of IC was improved by embedding a self-produced 8 kV-class (Chip level) ESD protection circuit of a P-substrate-Triggered Silicon Controlled Rectifier (PTSCR) type with high robustness characteristics.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.173-174
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• 2006

High power amplifier (HPA), which is used in transmitter of wireless communication systems, usually works in near saturation point in order to achieve maximum efficiency. In this region, HPA can introduce undesirable nonlinear effects. In this paper, we present a polynomial modeling method for efficient techniques to compensate for nonlinear distortion introduced by nonlinear HPA. Proposed polynomial predistorter inverses actual amplifier. Namely, we derive polynomials of amplifiers from analytical method and the electrical parameters in the data sheet of an actual amplifier and then can derive polynomial predistorter by inversing them. It is an effective and a simple method to compensate nonlinear distortion. SSPA(Solid-state power amplifier) is considered. We also analyze the effects of predistortion on the SER performance of communication system with 16-QAM modulation format. The results have shown the efficiency of this model.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1994년도 추계학술대회 논문집 학회본부
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• pp.141-143
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• 1994

The pulse width modulated class D power amplifier has the highest efficiency among various class amplifiers but the performances, such as bandwidth, distortion and stability are inferior to the conventional ones. In this paper, a new class D amplifier design is Presented employing dual feedback loops namely current and voltage feedback. The new design provides wide full-power bandwidth and stability at any load with high efficiency.

• 전자공학회논문지B
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• 제33B권3호
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• pp.47-55
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• 1996

An optical transmitter, which is a key component of the optical transmission system, converts the electrical signal to optical signal and consists of a high-speed current-pulse driver for laser diode and low-speed feedback loops that stabilize optical power against aging, power supply voltage fluctuations, and ambient temperature changes. In this paper, the power-stabilizing part, which forms the bulk of the optical transmitter circuitry was designed in integrted circuits. Operational amplifiers and reference voltage generation circuits, which were identified as key building blocks for the power-stabilizing feedback loops, were designed and were subsequently verified through HSPICE simulations. The designed operational amplifier consists of a two-stage folded cascode amplifier and class AB output stage, whereas the reference voltage is obtained by bandgap reference circuits. Finally the power-stabilizing circuitry was laid out based on 3\mu$m CMOS design rules for fabrication.

• 전기학회논문지P
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• 제52권1호
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• pp.28-34
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• 2003

In this paper, a predistortion linearizer using series diode is proposed for linearizing the power amplifier in microwave radio systems. The power amplifier should be operated near saturation region to achieve high efficiency. But at this region, amplitude and phase distortions of the amplifier remarkably increase with the increase of input power and cause a significant adjacent channel interference. The linearizer is composed of a series diode with a parallel capacitor, which provides positive amplitude and negative phase deviations with the increasing input power. This type of linearizer using the nonlinearity of diode has improved the C/I(Carrier to Intermodulation Distortion) ratio well. By applying this linearizer to two-tone 880MHz power amplifier, adjacent channel leakage power is improved up to 5dBm.

• 전자공학회논문지D
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• 제34D권10호
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• pp.24-31
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• 1997

A new design method of stable RF power amplifier using 3dB coupled line is proposed in this thiesis. The proposed method of broadband matching consist of resistive matching circuits at low frequency and lossless matching circuits at microwave band. This design method increase the stability of an amplifier and is suitable for interstage matching. When high power amplifier is designed using this method for PCS base transceiver station, the measured resutls show thst the gain of 18.5dB, and 9W (39.5dBm) output power. We use motorola's MRF6401 for medium power and MRF 6402 for large power and cascaded them.