• Journal of the Korea Academia-Industrial cooperation Society
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• v.7 no.2
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• pp.126-130
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• 2006

Programmable Logic Controller(PLC) is the most widely utilized and plays an important role in industrial control system. Sequential Function Chart(SFC) is a graphic language which is suitable for describing a sequential control logic in discrete control system. We can design a distribute control construction and a hierarchical control construction in process control system described by SFC. In hierarchical control structure, we construct each subsystems to synchronize a synchronous signal between subsystems, and the command system gives and takes a synchronous signal with subsystems. Therefore, the system has a low memory efficiency and a low system performance. In this paper, we propose the method that improved the efficiency of memory in hierarchical control construction, and confirm its feasibility through an actual example.

• The Journal of the Korea Contents Association
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• v.14 no.3
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• pp.22-32
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• 2014

Recently, GPGPU has been widely used for general-purpose processing as well as graphics processing by providing optimized hardware for parallel processing. Memory system has big effects on the performance of parallel processing units such as GPU. In the GPU, hierarchical memory architecture is implemented for high memory bandwidth. Moreover, both memory address coalescing and memory request merging techniques are widely used. This paper analyzes the GPU performance according to various memory organizations. According to our simulation results, GPU performance improves by 15.5%, 21.5%, 25.5%, 30.9% as adding 8KB L1, 16KB L1, 32KB L1, 64KB L1 cache, respectively, compared to case without L1 cache. However, experimental results show that some benchmarks decrease performance since memory transaction increases due to data dependency. Moreover, average memory access latency is increased as the depth of hierarchical cache level increases when cache miss occurs significantly.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.694-698
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• 2004

In this paper, as one of these efforts for making the intelligent data mining system we propose the Associative frame of the memory according to the following three steps. First,the structured frame for performing the main brain function should be made. In this frame, the concepts of learning memory and episode memory are considered. Second,the learning mechanism for data acquisition and storing mechanism in the memory frame are provided. The obtained data are arranged and stored in the memory following the rules of the structured memory frame. Third, it is the last step of processing the inference and knowledge retrieval function using the stored knowledge in the associative memory frame. This system is applied to the area for estimating the purchasing degree from the type of customer's tastes, the pattern of commodities and the evaluation of a company.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.6
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• pp.901-909
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• 1990

With a wide spread of 32 bit personal computers, a simple structure and high performance memory system have been highly required. In this paper, a memory block is constructed by using a modified hierarchical bit line in which the DRAM bit line and the latch which works as a SRAM cell are integrated by an interface gate. And the new architecture memory DSRAM(Dynamic Static RAM) is proposed by interleaving the 16 memory block. Because the DSRAM works with 16 page, the page is miss ratio becomes small and the RAS precharge time which is incurred by page miss is shortened. So the DSRAM can implement an optimum page interleaving and it has good compatibility to the existing DRAMs. The DSRAM can be widely used in small computers as well as a high performance memory system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.9
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• pp.14-24
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• 2009

Memory cell array and peripheral circuits are designed for system on panel style frame buffer. Moreover, a parallel test methodology to test multiple blocks of memory cells is proposed to overcome low yield of system on panel processing technologies. It is capable of faster fault detection compared to conventional memory tests and also applicable to the tests of various embedded memories and conventional SRAMs. The various patterns of conventional test vectors can be used to enhance fault coverage. The proposed testing method is also applicable to hierarchical bit line and divided word line, one of design trends of recent memory architectures.

• Smart Media Journal
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• v.3 no.1
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• pp.33-38
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• 2014

Even though the performance of microprocessor is improved continuously, the performance improvement of computing system becomes hard to increase, in order to some drawbacks including increased power consumption. To solve the problem, general-purpose computing on graphics processing units(GPGPUs), which execute general-purpose applications by using specialized parallel-processing device representing graphics processing units(GPUs), have been focused. However, the characteristics of applications related with graphics is substantially different from the characteristics of general-purpose applications. Therefore, GPUs cannot exploit the outstanding computational resources sufficiently due to various constraints, when they execute general-purpose applications. When designing GPUs for GPGPU, memory system is important to effectively exploit the GPUs since typically general-purpose applications requires more memory accesses than graphics applications. Especially, external memory access requiring long latency impose a big overhead on the performance of GPUs. Therefore, the GPU performance must be improved if hierarchical memory architecture which can reduce the number of external memory access is applied. For this reason, we will investigate the analysis of GPU performance according to hierarchical cache architectures in executing various benchmarks.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.37 no.5
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• pp.261-271
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• 1988

This paper presents a hierarchical algorithm of the measurement system design by system partitioning. With the increase of system size, the conventional algorithms of the optimal measurement system design confront the problems of excessive memory requirements, long computation time and cumulative computation errors. In order to overcome these problems, a hierarchical approach by system partitioning is proposed with the introduction of equivalent measurements for all the extemal measurements. This approach has the advantage of remarkable reduction in computation time and memory requirements, and guarantees sufficient calculation accuracy in its application to large power systems. The proposed algorithm has been tested for various systems, which shows its applicability to practical power systems.

• Journal of IKEEE
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• v.8 no.2 s.15
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• pp.207-215
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• 2004

In a hierarchical-bus multiprocessor system, cache coherence protocol has effect on system performance. Under a particular cache coherence protocol, system performance can be affected by bus bandwidth, memory size, and memory block size. Therefore sensitivity analysis is necessary for the part of multiprocessor system. In this paper, we set up cache coherence protocol for hierarchical-bus multiprocessor system, and compute probability of state of protocol, and analyze sensitivity for part of system by simulation.

• The Transactions of the Korea Information Processing Society
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• v.3 no.6
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• pp.1433-1442
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• 1996

Data distribution of SPMD(Single Program Multiple Data) pattern is one of main features of HPF (High Performance Fortran). This paper describes design is sues for such data distribution and its efficient execution model on TICOM IV computer, named SPAX(Scalable Parallel Architecture computer based on X-bar network). SPAX has a hierarchical clustering structure that uses distributed shared memory(DSM). In such memory structure, it cannot make a full system utilization to apply unanimously either SMDD(shared Memory Data Distribution) or DMDD(Distributed Memory Data Distribution). Here we propose another data distribution model, called DSMDD(Distributed Shared Memory Data Distribution), a data distribution model based on hierarchical masters-slaves scheme. In this model, a remote master and slaves are designated in each node, shared address scheme is used within a node and message passing scheme between nodes. In our simulation, assuming a node size in which system performance degradation is minimized,DSMDD is more effective than SMDD and DMDD. Especially,the larger number of logical processors and the less data dependency between distributed data,the better performace is obtained.

• Journal of Korea Multimedia Society
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• v.12 no.12
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• pp.1718-1727
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• 2009

Traditional character recognition systems usually aim at characters with simple variation. With the development of multimedia technology, printed characters may appear more diversely. Existing recognition technologies can't deal with Hangul recognition effectively in diverse environments. This paper presents a recognition system for multi-form Korean characters called RSMFK, which is based on the model of Hierarchical Temporal Memory (HTM). Our system can effectively recognize the printed Korean characters of different fonts, scales, rotation, noise and background. HTM is a model which simulates the neocortex of human brain to recognize and memorize intelligently. Experimental results show that RSMFK performs a good recognition rate of 97.8% on average, which is proved to be obviously improved over the conventional methods.