• The Transactions of the Korean Institute of Power Electronics
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• v.23 no.4
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• pp.231-239
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• 2018

The phase-locked loop (PLL) is widely used in grid-tie inverter applications to achieve a synchronization between the inverter and the grid. However, its performance deteriorates when the grid voltage is not purely sinusoidal due to the harmonics and the frequency deviation. Therefore, a high-performance PLL must be designed for single-phase inverter applications to guarantee the quality of the inverter output. This paper proposes a simple method that can improve the performance of the PLL for the single-phase inverter under a non-sinusoidal grid voltage condition. The proposed PLL can accurately estimate the fundamental frequency and theta component of the grid voltage even in the presence of harmonic components. In addition, its transient response is fast enough to track a grid voltage within two cycles of the fundamental frequency. The effectiveness of the proposed PLL is confirmed through the PSIM simulation and experiments.

• Proceedings of the KIPE Conference
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• 2017.11a
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• pp.7-8
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• 2017

The Phase-Locked Loop (PLL) is widely used in grid-tie inverter applications to achieve the synchronization between the inverter and the grid. However, its performance is deteriorated when the grid voltage is not pure sinusoidal due to the harmonics and the frequency deviation. Therefore it is important to design a high performance phase-locked loop (PLL) for the single phase inverter applications to guarantee the quality of the inverter output. In this paper a simple method to improve the performance of the PLL for the single phase inverter is proposed. The proposed PLL is able to accurately estimate the fundamental frequency component of the grid voltage even in the presence of harmonic components. In additional its transient response is fast enough to track a change in grid voltage within two cycles of the fundamental frequency. The effectiveness of the proposed PLL is confirmed through the PSIM simulation and experiments.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.10 no.6
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• pp.816-824
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• 1999

Design and performance of 18 GHz phase locked dielectric resonator oscillator(PLDRO) for Point-to-point radio link using analog phase locked loop is described which achieve high stability and low SSB phase noise. The module consists of an 18 GHz voltage controlled dielectric resonator oscillator(VCDRO), buffered amplifier, analog phase detector which are integrated to form a miniature hybrid circuit. In addition, containing a low phase noise VHF PLL has been designed to lock any other conventional N times frequency of crystal oscillator. The module achieves stable phase locked state, exhibits output power of 21 dBm at 18.00 GHz, -34 dBc harmonic suppression and -75 dBc/Hz phase noise at 10 kHz offset frequency from carrier.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.28 no.11
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• pp.68-76
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• 2014

This paper presents an offset error compensation algorithm for the accurate phase angle of the grid voltage in single-phase grid-connected inverters. The offset error generated from the grid voltage measurement process cause the fundamental harmonic component with grid frequency in the synchronous reference frame phase lock loop (PLL). As a result, the grid angle is distorted and the power quality in power systems is degraded. In addition, the dq-axis currents in the synchronous reference frame and phase current have the dc component, first and second order ripples compared with the grid frequency under the distorted grid angle. In this paper, the effects of the offset and scaling errors are analyzed based on the synchronous reference frame PLL. Particularly, the offset error can be estimated from the integrator output of the synchronous reference frame PLL and compensated by using proportional-integral controller. Moreover, the RMS (Root Mean Square) function is proposed to detect the offset error component. The effectiveness of the proposed algorithm is verified through simulation and experiment results.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.4
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• pp.39-50
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• 2011

In this paper, we presents a CDR circuit for $2^{nd}$-generation AiPi+, one of the Intra-panel Interface. The speed of the proposed clock and data recovery is increased to 1.25 Gbps compared with that of AiPi+. The DLL-based CDR architecture is used to generate the multi-phase clocks. We propose the simple scheme for frequency detector (FD) to mitigate the harmonic-locking and reduce the complexity. In addition, the duty cycle corrector that limits the maximum pulse width is used to avoid the problem of missing clock edges due to the mismatch between rising and falling time of VCDL's delay cells. The proposed CDR is implemented in 0.18 um technology with the supply voltage of 1.8 V. The active die area is $660\;{\mu}m\;{\times}\;250\;{\mu}m$, and supply voltage is 1.8 V. Peak-to-Peak jitter is less than 15 ps and the power consumption of the CDR except input buffer, equalizer, and de-serializer is 5.94 mW.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.2
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• pp.122-133
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• 2013

An arbiter-based simple phase decision circuit (PDC) optimized for high-resolution phase-to-digital converter made up of an analog phase-frequency detector and a time-to-digital converter for all-digital phase-locked loops is proposed. It can distinguish very small phase difference between two pulses even though it consumes lower power and has smaller input-to-output delay than the previously reported PDC. Proposed PDC is realized using 130-nm CMOS process and demonstrated by transistor-level simulations. A 5-bit P2D having no offset nor deadzone using the PDC is also demonstrated. A harmonic-lock-free and small-phase-offset delay-locked loop for fixing the P2D resolution regardless of PVT variations is also proposed and demonstrated.

• Journal of Electrical Engineering and Technology
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• v.9 no.3
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• pp.1104-1111
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• 2014

The digital substations are being built based on the IEC 61850 network. The cooperation and protection of power system are becoming more intelligent and reliable in the environment of digital substation. This paper proposes a novel method to prevent the malfunction caused by the Transformer Magnetizing Inrush Current(TMIC) using the IEC 61850 based data sharing between the IEDs. To protect a main transformer, the current differential protection(87T) and over-current protection(50/51) are used generally. The 87T IED applies to the second harmonic blocking method to prevent the malfunction caused by the TMIC. However, the 50/51 IED may malfunction caused by the TMIC. To solve that problem, the proposed method uses a GOOSE inter-lock signal between two IEDs. The 87T IED transmits a blocking GOOSE signal to the 50/51 IED, when the TMIC is detected. The proposed method can make a cooperation of digital substation protection system more intelligent. To verify the performance of proposed method, this paper performs the real time test using the RTDS (Real Time Digital Simulator) test-bed. Using the RTDS, the power system transients are simulated, and the TMIC is generated. The performance of proposed method is verified in real-time using that actual current signals. The reaction of simulated power system responding to the operation of IEDs can be also confirmed.

• International Journal of Naval Architecture and Ocean Engineering
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• v.12 no.1
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• pp.491-500
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• 2020

The present study proposes a time domain model for the Vortex-induced Vibration (VIV) simulation of a catenary riser under the combination of the current and oscillatory flow induced by vessel motion. In this model, the hydrodynamic force of VIV comprises excitation force, hydrodynamic damping and added mass, which are taken as functions of the non-dimensional frequency and amplitude ratio. The non-dimensional frequency is related with the response frequency, natural frequency, lock-in range and the fluid velocity. The relatively oscillatory flow induced by vessel motion is taken into account in the fluid velocity. Considering that the added mass coefficient and the non-dimensional frequency can affect each other, an iterative analysis is conducted at each time step to update the added mass coefficient and the natural frequency. This model is in detail validated against the published test models. The results show that the model can reasonably reflect the effect of the added mass coefficient on the VIV, and can well predict the riser's VIV under stationary and oscillatory flow induced by vessel motion. Based on the model, this study carries out the VIV simulation of a catenary riser with harmonic vessel motion. By analyzing the bending moment near the touchdown point, it is found that under the combination of the ocean current and oscillatory flow the vessel motion may decrease the VIV response, while increase the excited frequencies. In addition, the decreasing rate of the VIV under vessel surge is larger than that under vessel heave at small vessel motion velocity, while the situation becomes opposite at large vessel motion velocity.