• Journal of the Korean Institute of Intelligent Systems
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• v.9 no.6
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• pp.634-643
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• 1999

This paper concerns an implementation of f~rry logic controller (FLC') on a reconfigurahle FP

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.11
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• pp.29-36
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• 2003

In this paper, an efficient VLSI architecture for DCTQ module, which consists of 2D-DCT, quantization, AC/DC prediction block, scan conversion, inverse quantization and 2D-IDCT, is presented. The architecture of the module is designed to handle a macroblock data within 1064 cycles and suitable for MPEG-4 video codec handling 30 frame CIF image for both encoder and decoder simultaneously. Only single 1-D DCT/IDCT cores are used for the design instead of 2-D DCT/IDCT, respectively. 1-bit serial distributed arithmetic architecture is adopted for 1-D DCT/IDCT to reduce the hardware area in this architecture. To reduce the power consumption of DCTQ modu1e, we propose the method not to operate the DCTQ modu1e exploiting the SAE(sum of absolute error) value from motion estimation and cbp(coded block pattern). To reduce the AC/DC prediction memory size, the memory architecture and memory access method for AC/DC prediction block is proposed. As the result, the maximum utilization of hardware can be achieved, and power consumption can be minimized. The proposed design is operated on 27MHz clock. The experimental results show that the accuracy of DCT and IDCT meet the IEEE specification.

• Journal of Advanced Navigation Technology
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• v.8 no.2
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• pp.105-111
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• 2004

This paper describes the design of navigation system for an unmanned target drone which is operated by Korean army as for anti-air gun shooting training. Current target drone is operated by pilot control of on-board servo motor via remote control system. Automatic flight control system for the target drone greatly reduces work load of ground pilot and can increase application area of the drone. Most UAVs being operated nowdays use high-priced sensors as AHRS and IMU to measure the attitude, but those are costly. This paper introduces the development of low-cost automatic flight control system with low-cost sensors. The integrated automatic flight control system has been developed by integrating combining power module, switching module, monitoring module and RC receiver as an one module. The performance of navigation for low cost unmanned aerial vehicle, unmanned target drone as our test bed in this paper is verified by both Hardware in the loop simulation(HILS) to test performance of GPS as GPS output frequency high and results of flight test.

• Smart Media Journal
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• v.7 no.4
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• pp.9-16
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• 2018

In order to improve the economics and flexibility of cloud computing, tendency to automate the operation and management of cloud resources has become complicated. However, while automation for cloud storage depends on the manufacturer's storage hardware, it cannot flexibly support the storage type in accordance with users' needs. In this paper, we propose an automatic configuration module that supports block/file/object storages suitable for user environment. In order to automatically install ceph, a cloud storage, we propose an automatic installation and configuration module based on the Chef configuration management tool. In addition to that, we also propose an automatic configuration module based on a shell programming in pursuit of enabling users to use ceph storage of block/file/object. The proposed method can automatically set up and manage shared file, block, and object storages in a virtual or physical user environment with no hardware dependencies.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.12C
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• pp.1182-1191
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• 2003

In this paper, we propose a new hardware architecture for integer transform, quantizer, inverse quantizer, and inverse integer transform of a new video coding standard H.264/JVT. We describe the algorithm and derive hardware architecture emphasizing the importance of area for low cost and low power consumption. The proposed architecture has been verified by PCI-interfaced emulation board using APEX-II Alters FPGA and also by ASIC synthesis using Samsung 0.18 um CMOS cell library. The ASIC synthesis result shows that the proposed hardware can operate at 100 MHz, processing more than 1,300 QCIF video frames per second. The hardware is going to be used as a core module when implementing a complete H.264 video encoder/decoder ASIC for real-time multimedia application.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.67 no.1
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• pp.9-14
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• 2018

In this paper, we introduce an AES-based security chip for the embedded system of Internet of Things(IoT). We used Verilog HDL to implement the AES algorithm in FPGA. The designed AES module creates 128-bit cipher by encrypting 128-bit plain text and vice versa. RTL simulations are performed to verify the AES function and the theory is compared to the results. An FPGA emulation was also performed with 40 types of test sequences using two Altera DE0-Nano-SoC boards. To evaluate the performance of security algorithms, we compared them with AES implemented by software. The processing cycle per data unit of hardware implementation is 3.9 to 7.7 times faster than software implementation. However, there is a possibility that the processing speed grow slower due to the feature of the hardware design. This can be solved by using a pipelined scheme that divides the propagation delay time or by using an ASIC design method. In addition to the AES algorithm designed in this paper, various algorithms such as IPSec can be implemented in hardware. If hardware IP design is set in advance, future IoT applications will be able to improve security strength without time difficulties.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.5
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• pp.926-932
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• 2007

Various research groups proposed various architecture of hardware VPN for the high performance VPN system. However, the VPN based on hardware researcher are focused only on the encryption acceleration. Soft based VPN is only useful when the network connection is slow. We have to consider the hardware performance (encryption/decryption processing capability, packet processing, architecture method) to implement hardware based VPN. In this paper, we have analysed architecture of hardware, consideration and problems for high-speed VPN system, From the result, we can choose the proper design guideline.

• Journal of Applied Reliability
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• v.14 no.2
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• pp.97-102
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• 2014

Radar is an object-detection system that uses radio waves to determine the range, altitude, direction, or speed of objects. High power amplifier Module is the most critical part of the high-power radar transmitter systems. It can be used to detect aircraft, ships, spacecraft, guided missiles, motor vehicles, weather formations, and terrain. Research related to radar has been conducted in various fields according to improvement of the communication technology. But only performance-originated technology development has been dashed; study concerning environment duality and safety concerning reliability are still insufficient. In general, radar module is exposed to the outside, on the means of moving or fixed in a certain place. It should be guaranteed sufficient immunity for a variety of environmental stresses that can occur in the outdoor. HALT is a great process used for quickly finding failure mechanisms in a hardware design and product. By applying various kinds and extreme level of stresses, we can find the operating limits of products. In thesis, we conducted HALT test of the high power amplifier modules which used in military and automotive radar. After the test, we analyzed environmental weaknesses of high power amplifier modules using conventional construction data.

• Journal of Institute of Control, Robotics and Systems
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• v.17 no.6
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• pp.539-545
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• 2011

This paper describes an intelligent service robot system for managing a store in an unmanned environment. The robot can be a good replacement for humans because it is possible to work all day and to remember lots of information. We design a system architecture for configuring many intelligent functions of intelligent service robot system which consists of four layers; a User Interaction Layer, a Behavior Scheduling Layer, a Intelligent Module Layer, and a Hardware Layer. We develop an intelligent service robot 'Part Timer' based on the designed system architecture. The 'Part Timer' has many intelligent function modules such as face detection-recognition-tracking module, speech recognition module, navigation module, manipulator module, appliance control module, etc. The 'Part Timer' is possible to answer the phone and this function gives convenient interface to users.

• Journal of the Institute of Convergence Signal Processing
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• v.11 no.2
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• pp.177-182
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• 2010

The flow of a universal system-level design methodology consists of system specification, system-level hardware/software partitioning, co-design, co-verification using virtual or physical prototype, and system integration. In the developing process of a hardware component in system, the design phase has been regarded as a phase consuming lots of time and cost. However, the verification phase in which functionality of the designed component is verified has recently been considered as a much important phase. In this paper, the implementation of a verification environment which is based on SystemC infrastructure and verifies the functionality of a hardware component is described. The proposed verification system uses SystemC user-defined channel as communication interface between variables of SystemC module and registers of Verilog module. The functional verification of an UART is performed on the proposed verification system. SystemC provides class library for hardware modeling and has an advantage of being able to design a system consisting hardware and software in higher abstraction level than register transfer level. Source codes of SystemC modules are reusable with a minor adaptation on verifying functionality of another hardware component.