• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.7
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• pp.37-47
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• 2011

Real picture like high quality computer graphic is widely used in various fields and shader processor, a key part of a graphic processor, has been advanced to programmable unified shader. However, The existing graphic processors have been optimized to commercial algorithms, so development of an algorithm which is not based on it requires an independent shader processor. In this paper, we have designed and implemented a control unit to support high quality 3 dimensional computer graphic image on programmable integrated shader processor. We have done evaluation through functional level simulation of designed control unit. Hardware resource usage rate are measured by implementing directly on FPGA Virtex-4 and execution speed are verified by applying ASIC library. the result of an evaluation shows that the control unit has the commands more about 1.5 times compared to the other shader processors that is a behavior similar to the control unit and with a number of processing units used in a shader processor, compared with the other processors, overall performance of the control unit is improved about 3.1 GFLOPS.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.19-24
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• 2007

With recent advancement of high-speed, multi-gigabit data transmission capabilities, serial links have been more widely adopted in industry than parallel links. Since the parallel link design forces its transmitter to transmit both the data and the clock to the receiver at the same time, it leads to hardware's intricacy during high-speed data transmission, large power consumption, and high cost. Meanwhile, the serial links allows the transmitter to transmit data only with no synchronized clock information. For the purpose, clock and data recovery circuit becomes a very crucial key block. In this paper, a 5.4Gbps half-rate bang-bang CDR is designed for the applications of high-speed graphic DRAM interface. The CDR consists of a half-rate bang-bang phase detector, a current-mirror charge-pump, a 2nd-order loop filter, and a 4-stage differential ring-type VCO. The PD automatically retimes and demultiplexes the data, generating two 2.7Gb/s sequences. The proposed circuit is realized in 66㎚ CMOS process. With input pseudo-random bit sequences (PRBS) of $2^{13}-1$, the post-layout simulations show 10psRMS clock jitter and $40ps_{p-p}$ retimed data jitter characteristics, and also the power dissipation of 80mW from a single 1.8V supply.

• Journal of Engineering Education Research
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• v.10 no.3
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• pp.79-92
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• 2007

To enhance the excellence, effectiveness and economical efficiency in the learning process, we implement a hybrid educational system for engineering experiments where web-based virtual laboratory systems and distance education systems are properly integrated. In the first stage, we designed client/server distributed environment and developed web-based virtual laboratory systems for digital systems and electrical/electronic circuit experiments. The proposed virtual laboratory systems are composed of four important sessions and their management system: concept learning session, virtual experiment session, assessment session. With the aid of the management system every session is organically tied up together to achieve maximum learning efficiency. In the second stage, we have implemented efficient and cost-effective distant laboratory systems for practicing electric/electronic circuits, which can be used to eliminate the lack of reality occurred during virtual laboratory session. The use of simple and user-friendly design allows a large number of people to access our distant laboratory systems easily. Thus, self-guided advanced training is available even if a lot of expensive equipment will not be provided in the on-campus laboratories. The proposed virtual/distant laboratory systems can be used in stand-alone fashion, but to enhance learning efficiency we integrated them and developed a hybrid educational system for engineering experiments. Our hybrid education system provides the learners with interactive learning environment and a new approach for the delivery of engineering experiments.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.9 s.339
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• pp.51-60
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• 2005

The design of efficient cryptosystems is mainly appointed by the efficiency of the underlying finite field arithmetic. Especially, among the basic arithmetic over finite field, the rnultiplicative inversion is the most time consuming operation. In this paper, a fast inversion algerian in finite field $GF(2^m)$ with the standard basis representation is proposed. It is based on the Extended binary gcd algorithm (EBGA). The proposed algorithm executes about $18.8\%\;or\;45.9\%$ less iterations than EBGA or Montgomery inverse algorithm (MIA), respectively. In practical applications where the dimension of the field is large or may vary, systolic array sDucture becomes area-complexity and time-complexity costly or even impractical in previous algorithms. It is not suitable for low-weight and low-power systems, i.e., smartcard, the mobile phone. In this paper, we propose a new hardware architecture to apply an area-efficient and a synchronized inverter on low-complexity systems. It requires the number of addition and reduction operation less than previous architectures for computing the inverses in $GF(2^m)$ furthermore, the proposed inversion is applied over either prime or binary extension fields, more specially $GF(2^m)$ and GF(P) .

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.4
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• pp.63-72
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• 2007

In this paper, we propose a novel reconfigurable coprocessor for multimedia mobile terminals. Because most of multimedia operations require fast operations of large amount of data in the limited clock frequency, it is necessary to enhance the performance of the embedded processor that is widely used in current multimedia mobile terminals. Therefore, we proposed and have designed the coprocessor which had the ability of fast operations of multimedia data. The proposed coprocessor was not only reconfigurable, but also flexible and expandable. The proposed coprocessor has been designed by using VHDL and compared with previous reconfigurable coprocessors and a commercial embedded processor in architecture and speed. As a result of the architectural comparison, the proposed coprocessor had better structure in terms of hardware size and flexibility. Also, the simulation results of DCT application showed that the proposed coprocessor was 26 times faster than a commercial ARM processor and 11 times faster than the ARM processor with fast DCT core.

• Journal of Korea Game Society
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• v.8 no.3
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• pp.43-50
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• 2008

UI design is growing in meaning and form itself through the development of hardware and contents. And it makes users accept its interface as a extension of the body and mind because of the substantial rapport of the user and contents with developing of device and graphic. In this study, we analyzed user interface in a view of digital storytelling by observing of its role within user and contents. Not only this, classifying and investigating story elements in the games for forming the theoretical basis of storytelling UI are enforced. For the case study of UI, we choose the game, Diablo, Half-Life, and Homeworld because the game is suitable for the application of node-type storytelling and effectively uses graphic and input unit. This analysis explains the interface has the contents data that divided or shared and it means the interface performs its part of story nodes, which are extracted from the story, and choice. And we analogized that the story elemental can be substituted and used practically for interface because the stories made through the thing that users and developers are in the space of coexistence by the interface. Storytelling UI will be a good way to make a most intriguing piece as a joyful spontaneous complex that use story node. It is worth by reason of making by user and discovering live inner story so that it can approach to the substance of the story.

• Journal of Navigation and Port Research
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• v.29 no.1 s.97
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• pp.91-96
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• 2005

The National Marine Electronics Association(NMEA) is nonprofit-making cooperation composed with manufacturers, distributors, wholesalers and educational institutions. We use the basic port of equipment in order to process the signal from NMEA signal using equipment. When we don't have enough one, we use the multi-port for processing. However, we need to have module development simulation which could multiplex and provide NMEA related signal that we could solve the problems in multi-port application and exclusive equipment generation for a number of signal. For now, we don't have any case or product using NMEA multiplexer so that we import expensive foreign equipment or embody NMEA signal transmission program like software, using multi-port. These have problems since we have to pay lots ci money and build separate processing part for every application programs. Besides, every equipment generating NMEA signal are from different manufactures and have different platform so that it could cause double waste and loss of recourse. For making up for it, I suggest the NMEA multiplexer embodiment, which could independently move by reliable process and high performance single hardware module, improve the memory efficiency of module by designing the optimized Queue, and keep having reliability for realtime communication among the equipment such as main input sensor equipment Gyrocompass, Echo-sound, and GPS.

• Journal of Broadcast Engineering
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• v.25 no.1
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• pp.25-35
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• 2020

Recently, the development of image processing technology, as well as hardware performance, has been continuing the research on 3D point processing technology that provides users with free viewing angle and stereoscopic effect in various fields. Point cloud technology, which is a type of representation of 3D point, has attracted attention in various fields because it can acquired/expressed point precisely. However, since Hundreds of thousands, millions of point are required to represent one 3D point cloud content, there is a disadvantage that a larger amount of storage space is required than a conventional 2D content. For this reason, the MPEG (Moving Picture Experts Group), an international standardization organization, is continuing to research how to efficiently compress, store, and transmit 3D point cloud content to users. In this paper, a V-PCC bitstream generated by a V-PCC (Video-based Point Cloud Compression) encoder proposed by the MPEG-I (Immersive) group is composed of an MPU (Media Processing Unit) defined by the MMT. In addition, by extending the signaling message defined in the MMT standard, a parameter for a segmented transmission method of the 3D point cloud content by area and quality parameters considering the characteristic of the 3D point cloud content, so that the quality parameters can be selectively determined according to the user's request. Finally, in this paper, we verify the result through design/implementation of the verification platform based on the proposed technology.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.12
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• pp.867-879
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• 2006

This paper concerns fast and time accurate HW/SW cosimulation for MPSoC(Multi-Processor System-on-chip) architecture where multiple software and/or hardware components exist. It is becoming more and more common to use MPSoC architecture to design complex embedded systems. In cosimulation of such architecture, as the number of the component simulators participating in the cosimulation increases, the time synchronization overhead among simulators increases, thereby resulting in low overall cosimulation performance. Although SystemC cosimulation frameworks show high cosimulation performance, it is in inverse proportion to the number of simulators. In this paper, we extend the novel technique, called virtual synchronization, which boosts cosimulation speed by reducing time synchronization overhead: (1) SystemC simulation is supported seamlessly in the virtual synchronization framework without requiring the modification on SystemC kernel (2) Parallel execution of component simulators with virtual synchronization is supported. We compared the performance and accuracy of the proposed parallel SystemC cosimulation framework with MaxSim, a well-known commercial SystemC cosimulation framework, and the proposed one showed 11 times faster performance for H.263 decoder example, while the accuracy was maintained below 5%.

• KIPS Transactions on Computer and Communication Systems
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• v.7 no.1
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• pp.9-18
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• 2018

Enhancing performance of big data analytics in distributed environment has been issued because most of the big data related applications such as machine learning techniques and streaming services generally utilize distributed computing frameworks. Thus, optimizing performance of those applications at Spark has been actively researched. Since optimizing performance of the applications at distributed environment is challenging because it not only needs optimizing the applications themselves but also requires tuning of the distributed system configuration parameters. Although prior researches made a huge effort to improve execution performance, most of them only focused on one of three performance optimization aspect: application design, system tuning, hardware utilization. Thus, they couldn't handle an orchestration of those aspects. In this paper, we deeply analyze and model the application processing procedure of the Spark. Through the analyzed results, we propose performance optimization schemes for each step of the procedure: inner stage and outer stage. We also propose appropriate partitioning mechanism by analyzing relationship between partitioning parallelism and performance of the applications. We applied those three performance optimization schemes to WordCount, Pagerank, and Kmeans which are basic big data analytics and found nearly 50% performance improvement when all of those schemes are applied.