• Journal of Multimedia Information System
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• 제6권1호
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• pp.7-14
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• 2019

This work presents a virtual prototyping design approach for an area-based image stitching hardware. The virtual hardware obtained from virtual prototyping is equivalent to the conceptual algorithm, yet the conceptual blocks are linked to the actual circuit components including the memory, logic gates, and arithmetic units. Through the proposed method, the overall structure, size, and computation speed of the actual hardware can be estimated in the early design stage. As a result, the optimized virtual hardware facilitates the hardware implementation by eliminating trail design and redundant simulation steps to optimize the hardware performance. In order to verify the feasibility of the proposed method, the virtual hardware of an image stitching platform has been realized, where it required 10,522,368 clock cycles to stitch two $1280{\times}1024$ sized images. Furthermore, with a clock frequency of 250MHz, the estimated computation time of the proposed virtual hardware is 0.877sec, which is 10x faster than the software-based image stitch platform using MATLAB.

• 전자통신동향분석
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• 제36권6호
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• pp.78-87
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• 2021

Information technology (IT) has been applied to various fields, and currently, IT devices and systems are used in very important areas, such as aviation, industry, and national defense. Such devices and systems are subject to various types of malicious attacks, which can be software or hardware based. Compared to software-based attacks, hardware-based attacks are known to be much more difficult to detect. A hardware Trojan horse is a representative example of hardware-based attacks. A hardware Trojan horse attack inserts a circuit into an IC chip. The inserted circuit performs malicious actions, such as causing a system malfunction or leaking important information. This has increased the potential for attack in the current supply chain environment, which is jointly developed by various companies. In this paper, we discuss the future direction of research by introducing attack cases, the characteristics of hardware Trojan horses, and countermeasure trends.

• 정보과학회 논문지
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• 제44권4호
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• pp.344-351
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• 2017

속성 기반 서명은 속성을 가지는 서명키를 사용하여 속성 술어를 기반으로 하는 서명을 생성하는 암호 방식이다. 속성 기반 서명에서 서명을 생성하는 동안 서명키가 유출된다면, 해당 서명키에 대한 서명이 위조될 수 있는 문제가 발생한다. 따라서 서명 생성은 보안이 보장되는 하드웨어에서 수행되어야 한다. 이러한 하드웨어를 보안 하드웨어라고 명명한다. 그러나 보안 하드웨어는 연산속도가 느리기 때문에 속성 기반 서명과 같은 많은 연산을 빠른 시간 안에 수행하기에는 적합하지 않다. 이 논문은 속성 기반 서명의 연산을 분리하여 성능이 좋은 일반 하드웨어와 보안 하드웨어로 이루어지는 시스템에서 효율적으로 사용가능한 속성 기반 서명 기법을 제안한다. 제안하는 기법은 기존에 존재하는 임의의 속성 기반 서명과 일반 전자서명으로 설계가 가능하며, 속성 기반 서명이 안전하지 않은 환경에서 수행되더라도 일반 전자서명을 보안 하드웨어에서 수행함으로써 안전성을 보장한다. 제안된 논문은 기존의 속성 기반 서명을 보안 하드웨어에서 생성하는 것에 비해서 11배의 성능향상을 보인다.

• International Journal of Fuzzy Logic and Intelligent Systems
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• 제2권1호
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• pp.20-25
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• 2002

This paper presents a genetic programming based evolutionary strategy for on-line adaptive learnable evolvable hardware. Genetic programming can be useful control method for evolvable hardware for its unique tree structured chromosome. However it is difficult to represent tree structured chromosome on hardware, and it is difficult to use crossover operator on hardware. Therefore, genetic programming is not so popular as genetic algorithms in evolvable hardware community in spite of its possible strength. We propose a chromosome representation methods and a hardware implementation method that can be helpful to this situation. Our method uses context switchable identical block structure to implement genetic tree on evolvable hardware. We composed an evolutionary strategy for evolvable hardware by combining proposed method with other's striking research results. Proposed method is applied to the autonomous mobile robots cooperation problem to verify its usefulness.

• 한국신뢰성학회:학술대회논문집
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• 한국신뢰성학회 2011년도 춘계학술발표대회 논문집
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• pp.271-279
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• 2011

Automotive safety integrity level of hardware components can be achieved by satisfying quantitative and qualitative requirements. Based on ASIL, quantitative requirements are composed of hardware architectural metrics and evaluation of safety goal violations due to random hardware failures in ISO 26262. In this paper, the types of hardware failures will be defined and classified. Based on various metrics related with hardware failures, design essentials to achieve hardware safety integrity will be studied specifically. Issues associated with hardware development and assessment process are presented briefly.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권1호
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• pp.802-805
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• 2007

A hardware architecture is presented of a wavelet based multiple line addressing driving scheme for passive matrix displays using the FPGA (Field Programmable Gate Arrays), which will be integrated in the scalable video coding $architecture^{[1]}$. The incoming compressed video data stream will then directly be transformed to the required column voltages by the hardware architecture without the need of employing the video decompression.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2007년도 하계종합학술대회 논문집
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• pp.463-464
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• 2007

This paper presents the hardware-based genetic algorithm, written in VHDL. Due to parallel computation and no function call overhead, a hardware-based GA advantage a speedup over a software-based GA. The proposed architecture is constructed on a field-programmable gate arrays, which are easily reconfigured. Since a general-purpose GA requires that the fitness function be easily changed, the hardware implementation must exploit the reprogrammability.

• 한국산학기술학회논문지
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• 제13권2호
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• pp.755-759
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• 2012

본 논문에서는 의학, 게임분야에서 활용되는 하드웨어 기반의 난수 발생기에 관한 것이다. 인텔은 하드웨어 기반 실난수 발생기의 보안성에 대한 가이드라인을 제시한 바 있다. 주로 존슨 열 잡음원을 사용하며, 듀얼 오실레이터나 폰 노이만 수집기를 적용하고 있다. 하드웨어 기반의 난수 발생기는 NIST 통계검정, FIPS140-1을 포함한 다양한 테스트 유형을 적용하고 있다. 본 논문에서는 하드웨어 잡음원의 출력열에 필터링 기법 영향으로부터 난수성 변화 정도를 측정하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 하계종합학술대회논문집
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• pp.819-822
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• 1998

The high complexity of digital circuits has changed the digital circuits design mehtods from schemeatic-based to hardware description languages like VHDL, verilog that make hardware faults become more hard to detect. Thus test generation to detect hardware defects is very important part of the design. But most of the test generation methods are gate-level based. In this paper new high-level test generation method to detect stuck-at-faults on gate level is described. This test generation method is independent of synthesis results and reduce the time and efforts for test generation.

• 한국정보통신학회논문지
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• 제24권8호
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• pp.1109-1112
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• 2020

This paper presents a low cost hardware message passing engine of enhanced atomic pipelined broadcast based on processing node status. In this algorithm, the previous atomic pipelined broadcast algorithm is modified to reduce the waiting time until next broadcast communication. For this, the processor change the transmission order of processing nodes based on the nodes' communication channel. Also, the hardware message passing engine architecture of the proposed algorithm is modified to be adopted to multi-core processor. The synthesized logic area of the proposed hardware message passing engine was reduced by about 16%, compared by the pre-existing hardware message passing engine.