• The Transactions of the Korean Institute of Electrical Engineers D
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• v.53 no.12
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• pp.804-810
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• 2004

There are two important things for the general purpose neural network processor. The first is a capability to build various structures of neural network, and the second is to be able to support suitable learning method for that neural network. Some way to process various learning algorithms is required for on-chip learning, because the more neural network types are to be handled, the more learning methods need to be built into. In this paper, an improved hardware structure is proposed to compute various kinds of learning algorithms flexibly. The hardware structure is based on the existing modular neural network structure. It doesn't need to add a new circuit or a new program for the learning process. It is shown that rearrangements of the existing processing elements can produce several neural network learning modules. The performance and utilization of this module are analyzed by comparing with other neural network chips.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.353-356
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• 2002

In this paper, we design an efficient, scalable one-dimensional discrete wavelet transform (1DDWT) filter using data reorder unit (DRU). At each level, the required hardware is optimized by sharing multipliers and adders because the input rate is reduced by a factor of two at each level due to decimation. The proposed architecture shows 100% hardware utilization by balancing hardware with input rate. Furthermore, sharing the coefficients of the highpass and the lowpass filters using the mirror filter property reduces the number of multipliers and adders by half. We designed a scalable DRU that efficiently reorders and feeds inputs to highpass and lowpass filters. The proposed DRU-based architecture is so regular and scalable that it can be easily extended to an arbitrary 1D DWT structure with M taps and J levels. Compared to other architectures, the proposed DWT filter shows efficiency in performance with relatively less hardware.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.5
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• pp.162-167
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• 1994

The binary image normalization method in image processing can be used in several fields, Especially, its high speed processing method and its hardware implmentation is more useful, A normalization process of each character in character recognition requires a lot of processing time. Therefore, the research was done as a part of high speed process of OCR (optical character reader) implementation as a pipeline structure with host computer in hardware to give temporal parallism. For normalization process, general purpose CPU,MC68000, was used to implement it. As a result of experiment, the normalization speed of the hardware is sufficient to implement high speed OCR which the recognition speed is over 140 characters per second.

• Journal of Korea Multimedia Society
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• v.20 no.2
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• pp.289-297
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• 2017

When implementing a hardware elliptic curve cryptosystem (ECC) module, the efficient design of Modular Inverse (MI) algorithm is especially important since it requires much more computation than other finite field operations in ECC. Among the MI algorithms, binary Right-Shift modular inverse (RS) algorithm has good performance when implemented in hardware, but Montgomery Modular Inverse (MMI) algorithm is not considered in [1, 2]. Since MMI has a similar structure to that of RS, we show that the area-improvement idea that is applied to RS is applicable to MMI, and that we can improve the speed of MMI. We designed area- and speed-improved MMI variants as hardware modules and analyzed their performance.

• IEMEK Journal of Embedded Systems and Applications
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• v.6 no.4
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• pp.243-248
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• 2011

A FFT/IFFT processor is the key component for orthogonal frequency division multiplexing (OFDM) systems based IEEE 802.11n wireless local area network (WLAN). There exists many radix algorithms according to the structure of butterfly as FFT sub-module, each has the pros and cons on hardware complexity. Here, mixed radix algorithms for 64 and 128 FFT/IFFT processors are proposed, which reduce hardware complexity by using mixture of radix-23 and radix-4 algorithms. The proposed algorithm finish calculation within 3.2${\mu}s$ in order to meet IEEE 802.11n standard requirements and it has less hardware complexity compared with conventional algorithms.

• Nuclear Engineering and Technology
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• v.53 no.2
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• pp.688-694
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• 2021

The aim of this work is the analysis, design and hardware implementation of the fractional-order point kinetics (FNPK) model along with its closed-loop controller. The stability and closed-loop control of FNPK models are critical issues. The closed-loop stability of the controller-plant structure is established. Further, the designed PI/PD controllers are implemented in real-time on a DSP processor. The simulation and real-time hardware studies confirm that the designed PI/PD controllers result in a damped stable closed-loop response.

• Electronics and Telecommunications Trends
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• v.33 no.6
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• pp.107-117
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• 2018

In recent years, with the development of autonomous driving technology, high-performance artificial intelligence computing hardware platforms have been developed that can process multi-sensor data, object recognition, and vehicle control for autonomous vehicles. Most of these hardware platforms have been developed overseas, such as NVIDIA's DRIVE PX, Audi's zFAS, Intel GO, Mobile Eye's EyeQ, and BAIDU's Apollo Pilot. In Korea, however, ETRI's artificial intelligence computing platform has been developed. In this paper, we discuss the specifications, structure, performance, and development status centering on hardware platforms that support autonomous driving rather than the overall contents of autonomous driving technology.

• Journal of the Korea Furniture Society
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• v.18 no.2
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• pp.91-99
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• 2007

Modernity which is superficial phenomenon set off the mass scale for mass consumption and provide uniformly artificial environment. But natural destruction, environment pollution, resources exhaustion and so on has been caused by this and now ecology is threatened by destruction and damage beyond the limitation and human beings survival is even threatened. Accordingly furniture development for environment preservation considered environment problem is the urgent real situation. Recent paradigm is the concept of Eco-design which is the green design possible to live together in symbiosis, and new types of alternative furniture are needed in Korea as well. 'Furniture for disassembly' is presented as new method for alternative furniture. Furniture for disassembly can be presented by mainly two directions. The first main characteristic is what is assembled by the use of woodworking joints technique as an assembly structure system without any hardware. The second is what is presented as the structure possible to be assembled by simple manual tools with hardware without any glue. The advantages of furniture for disassembly are environment preservation, space application, transportation efficiency and shapeliness. In manufacture method which is different from present furniture, the application of traditional truss technique which uses various types of custom-made and connection technique in case of assemble structure system without hardware is the typical differences. This assembly method expects not only interest induction about assembly and disassembly of diagram per sub materials but also the development of emotion, the improvement of collaboration, space perception ability and shape sense, the improvement of solid body structure insight and so on, when it use in the furniture for children with the application to many kinds of structure with BANGDOOSANJ (Wedged), JUMUGJANGBU (Dovetail) or NABIEUNJANG (Dovetail Keys) and so on.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.4
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• pp.765-770
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• 2012

In this paper, we proposed an effective hardware structure using DCT-based inra-prediction mode selection to reduce computational complexity caused by intra mode decision. In this hardware structure, the input block is transformed at first and then analyzed to determine its texture directional tendency. the complexity has solved by performing intra prediction in only predicted edge direction. $4{\times}4$ DCT is calculated in one cycle using Multitransform_PE and Inta_pred_PE calculates one prediction mode in two cycles. Experimental results show that the proposed Intra prediction encoding needs only 517 cycles for one macroblock encoding. This architecture improves the performance by about 17% than previous designs. For hardware implementation, the proposed intra prediction encoder is implemented using Verilog HDL and synthesized with Megnachip $0.18{\mu}m$ standard cell library. The synthesis results show that the proposed architecture can run at 125MHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.3
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• pp.585-593
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• 2017

In this paper, we propose a deblocking filter hardware architecture for low-power HEVC (High-Efficiency Video Coding) in-loop for mobile systems. HEVC performs image compression on a block-by-block basis, resulting in blockage of the image due to quantization error. The deblocking filter is used to remove the blocking phenomenon in the image. Currently, UHD video service is supported in various mobile systems, but power consumption is high. The proposed low-power deblocking filter hardware structure minimizes the power consumption by blocking the clock to the internal module when the filter is not applied. It also has four parallel filter structures for high throughput at low operating frequencies and each filter is implemented in a four-stage pipeline. The proposed deblocking filter hardware structure is designed with Verilog HDL and synthesized using TSMC 65nm CMOS standard cell library, resulting in about 52.13K gates. In addition, real-time processing of 8K@84fps video is possible at 110MHz operating frequency, and operation power is 6.7mW.