• 전자공학회논문지A
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• 제33A권7호
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• pp.261-268
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• 1996

Hardware-software codesign becomes improtant to effectively sagisfy perfomrance goals, because designers can trade-off in the way hardware and software components work teogether to exhibit a specified behavior. In this paper, a hardware-software pratitioning algorithm is presetned, in which the system behavioral description containing a mixture of hardware and software components is partitioned into hardware part and software part. The partitioning algorithm tries to minimize the given cost function under constraints on hardware resources or latency. Recursive moving of operations between the hardware and software parts is used to find a near optimum partition and the list scheduling approach is used to estimate the hardware area and latency. Since memory may take substantial protion of the hardware part, memory cost is included in sthe hardware cost. Experimental resutls show that our algorithm is effective.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제16권8호
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• pp.2816-2830
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• 2022

Number Theoretic Transform (NTT) is a method to design efficient multiplier for large integer multiplication, which is widely used in cryptography and scientific computation. On top of that, it has also received wide attention from the research community to design efficient hardware architecture for large size RSA, fully homomorphic encryption, and lattice-based cryptography. Existing NTT hardware architecture reported in the literature are mainly designed based on radix-2 NTT, due to its small area consumption. However, NTT with larger radix (e.g., radix-4) may achieve faster speed performance in the expense of larger hardware resources. In this paper, we present the performance evaluation on NTT architecture in terms of hardware resource consumption and the latency, based on the proposed radix-2 and radix-4 technique. Our experimental results show that the 16-point radix-4 architecture is 2× faster than radix-2 architecture in expense of approximately 4× additional hardware. The proposed architecture can be extended to support the large integer multiplication in cryptography applications (e.g., RSA). The experimental results show that the proposed 3072-bit multiplier outperformed the best 3k-multiplier from Chen et al. [16] by 3.06%, but it also costs about 40% more LUTs and 77.8% more DSPs resources.

• 경영과정보연구
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• 제2권
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• pp.133-167
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• 1998

This article discusses the findings of an empirical study conducted on 62 large organizations. The major purpose of the study was to analyze the relationship of Information System Resources distribution between the system plan control and system development and system operation. In this study information system resource is broadly Identified by computer hardware, software, data, procedure, operator. Because of the real centralization/decentralization issue facing organizations is much broader then the choice between alternative computer hardware configurations. And there are three separate resources of the information system that can be decentralized system plan and control, system development, system operations. The decision regarding how to organize each of these three separate resources is based on a different set of criteria. Furthermore, each decision can be made relatively independently of the others. In this article the results of a study are indicated below. In the degree of decentralization of information system resources between system plan control and system development and system operations were found the positive relationship. Therefore, the more information system resources are decentralized in the one dimension, the more information system resources are decentralized in the other dimensions, and the more information system resources are centralized in the one dimension, the more information system resources are centralized in the other dimensions.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권4호
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• pp.407-418
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• 2014

As the high-throughput requirement in the next generation communication system increases, it becomes essential to implement high-throughput SISO (Soft-Input Soft-Output) decoder with minimal hardware resources. In this paper, we present the comparison results between cascaded radix-4 ACS (Add-Compare-Select) and LUT (Look-Up Table)-based radix-4 ACS in terms of delay, area, and power consumption. The hardware overhead incurred from the retiming technique used for high speed radix-4 ACS operation is also analyzed. According to the various analysis results, high-throughput radix-4 SISO decoding architecture based on simple path metric recovery circuit is proposed to minimize the hardware resources. The proposed architecture is implemented in 65 nm CMOS process and memory requirement and power consumption can be reduced up to 78% and 32%, respectively, while achieving high-throughput requirement.

• 전기전자학회논문지
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• 제25권1호
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• pp.10-14
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• 2021

본 논문에서는 기존 CIE1931 색 좌표계를 이용한 색상 보정 연산의 복잡성을 개선한 하드웨어를 제안한다. 기존 알고리즘은 연산 과정에서 큰 비트 수를 계산하기 위해 사용되는 4-Split Multiply 연산으로 인해 하드웨어가 커지는 단점이 있다. 제안하는 알고리즘은 기존 알고리즘의 정의된 R2X, X2R 연산을 미리 계산하여 하나의 행렬로 만들어 영상에 적용함으로써 연산량 감소와 하드웨어 크기 감소가 가능하다. Verilog로 설계된 하드웨어의 Xilinx 합성 결과를 비교함으로써 하드웨어 자원 감소와 4K 환경 실시간 처리를 위한 성능을 확인할 수 있다. 또한, FPGA 보드에서의 실행 결과를 제시함으로써 하드웨어 탑재 동작을 검증하였다.

• 전자공학회논문지
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• 제51권3호
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• pp.112-118
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• 2014

디지털 영상 확대를 위한 영상 스케일링은 고품질의 영상이 요구될수록 많은 수행시간 및 하드웨어 자원량이 요구된다. 본 논문에서는 적은 연산량 및 하드웨어 자원으로 고품질 영상을 생성하는 이중 선형-3차회선 보간법을 제안한다. 제안한 보간법은 4번의 선형 보간법과 1번의 3차회선 보간법으로 이루어진 선형-3차회선 보간법을 수평방향과 수직방향으로 각각 수행하는 구조이다. 실험결과, 제안하는 보간법은 PSNR과 수행시간 및 하드웨어 자원량 측면에서 비교했을 때, 적은 연산량 및 하드웨어 자원으로 양 3차회선 보간법보다 우수한 PSNR을 제공했다.

• Journal of Information Processing Systems
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• 제15권6호
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• pp.1406-1421
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• 2019

The Internet-of-Things (IoT) has been deployed in almost every facet of our day to day activities. This is made possible because sensing and data collection devices have been given computing and communication capabilities. The devices implement System-on-Chips (SoCs) that incorporate a lot of functionalities, yet they are severely constrained in terms of memory capacitance, hardware area, and power consumption. With the increase in the functionalities of sensing devices, there is a need for low-cost synthesizable processors to handle control, interfacing, and error processing. The first step in selecting a synthesizable processor core for low-cost devices is to examine the hardware resource utilization to make sure that it fulfills the requirements of the device. This paper gives an analysis of the hardware resource usage of ten synthesizable processors that implement the Reduced Instruction Set Computer Five (RISC-V) Instruction Set Architecture (ISA). All the ten processors are synthesized using Vivado v2018.02. The maximum frequency, area, and power reports are extracted and a comparison is made to determine which processor is ideal for low-cost hardware devices.

• 대한전기학회논문지:시스템및제어부문D
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• 제49권3호
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• pp.133-144
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• 2000

Genetic Algorithm(GA) has been known as a method of solving large-scaled optimization problems with complex constraints in various applications. Since a major drawback of the GA is that it needs a long computation time, the hardware implementations of Genetic Algorithm Processors(GAP) are focused on in recent studies. In this paper, a hardware-oriented GA was proposed in order to save the hardware resources and to reduce the execution time of GAP. Based on steady-state model among continuos generation model, the proposed GA used modified tournament selection, as well as special survival condition, with replaced whenever the offspring's fitness is better than worse-fit parent's. The proposed algorithm shows more than 30% in convergence speed over the conventional algorithm in simulation. Finally, by employing the efficient pipeline parallelization and handshaking protocol in proposed GAP, above 30% of the computation speed-up can be achieved over survival-based GA which runs one million crossovers per second (1㎒), when device speed and size of application are taken into account on prototype. It would be used for high speed processing such of central processor of evolvable hardware, robot control and many optimization problems.

• Nuclear Engineering and Technology
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• 제53권2호
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• pp.688-694
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• 2021

The aim of this work is the analysis, design and hardware implementation of the fractional-order point kinetics (FNPK) model along with its closed-loop controller. The stability and closed-loop control of FNPK models are critical issues. The closed-loop stability of the controller-plant structure is established. Further, the designed PI/PD controllers are implemented in real-time on a DSP processor. The simulation and real-time hardware studies confirm that the designed PI/PD controllers result in a damped stable closed-loop response.

• 대한전자공학회논문지SD
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• 제47권3호
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• pp.35-40
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• 2010

본 논문에서는 저비용, 저전력 카메라 폰 구현을 위한 하드웨어 자원 공유가 가능한 구조의 카메라 제어 프로세서를 제안한다. 제안한 카메라 제어 프로세서의 구조는 내부에 직접 접근 경로를 내장함으로써 베이스 밴드 프로세서가 카메라 제어 프로세서의 하드웨어 자원을 직접 활용할 수 있도록 하여 베이스 밴드 프로세서의 기능 확장과 성능 향상을 도모하는데 그 목적이 있다. 또한, 제안한 구조와 결합하여 블록 단위 클럭 차단 기법을 적용하여 저전력 소비를 구현한 결과를 기술하였다. 따라서 제안한 카메라 제어 프로세서는 시스템의 하드웨어 자원 효율성을 향상시켜 저전력, 저비용 카메라 폰 시스템 구현을 가능하게 한다. 제안한 카메라 제어 프로세서는 0.18um CMOS 공정을 사용하여 제작되었으며 면적은 $3.8mm\;{\times}\;3.8mm$이다.