• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.10a
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• pp.401-404
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• 2016

This paper proposes entropy coding method of HEVC CABAC Encoder for efficient hardware architecture. The Binary Arithmetic Encoder requires data dependency at each step, which is difficult to be operated in a fast. Proposed Binary Arithmetic Encoder is designed 4 stage pipeline to quickly process the input value bin. According to bin approach, either MPS or LPS is selected and the binary arithmetic encoding is performed. Critical path caused by repeated operation is reduced by using the LUT and designed as a shift operation which decreases hardware size and not using memory. The proposed Binary Arithmetic Encoder of CABAC is designed using Verilog-HDL and it was implemented in 65nm technology. Its gate count is 3.17k and operating speed is 1.53GHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.3
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• pp.499-508
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• 2017

A new digital pre-distortion technique to linearize power amplifier (PA) is proposed for concurrent dual-band transmitters. In the conventional dual-band DPD techniques, two independent dual-feedback paths are required to compensate nonlinear cross-products between different bands as well as the nonlinear self-products of each band's own signal. However, it increases hardware complexity and expense. In this paper, we propose a new DPD method requiring only a single feedback path. In this new structure, the proposed technique first estimates the dual-band PA characteristics using the single feedback path. The DPD parameters are then extracted from the estimated PA characteristics. The DPD performance of the proposed method is validated through computer simulation. According to the results, the proposed technique can achieve comparable performance to the conventional two feedback DPD with significantly reduced hardware complexity.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.12
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• pp.1609-1617
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• 2019

Described in this paper is a design of hardware accelerator for implementing public-key cryptographic protocols (PKCPs) based on Elliptic Curve Cryptography (ECC) and RSA. It supports five elliptic curves (ECs) over GF(p) and three key lengths of RSA that are defined by NIST standard. It was designed to support four point operations over ECs and six modular arithmetic operations, making it suitable for hardware implementation of ECC- and RSA-based PKCPs. In order to achieve small-area implementation, a finite field arithmetic circuit was designed with 32-bit data-path, and it adopted word-based Montgomery multiplication algorithm, the Jacobian coordinate system for EC point operations, and the Fermat's little theorem for modular multiplicative inverse. The hardware operation was verified with FPGA device by implementing EC-DH key exchange protocol and RSA operations. It occupied 20,800 gate equivalents and 28 kbits of RAM at 50 MHz clock frequency with 180-nm CMOS cell library, and 1,503 slices and 2 BRAMs in Virtex-5 FPGA device.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.6 no.9
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• pp.2388-2404
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• 2012

Cryptographic hash functions are widely used in many information security applications like digital signatures, message authentication codes (MACs), and other forms of authentication. In response to recent advances in cryptanalysis of commonly used hash algorithms, National Institute of Standards and Technology (NIST) announced a publicly open competition for selection of new standard Secure Hash Algorithm called SHA-3. One important aspect of this competition is evaluation of hardware performances of the candidates. In this work we present efficient hardware implementations of SHA-3 finalists: JH, Keccak and Skein. We propose high speed architectures using Look-Up Table (LUT) resources on FPGAs, to minimize chip area and to reduce critical path lengths. This approach allows us to design data paths of SHA-3 finalists with minimum resources and higher clock frequencies. We implemented and investigated the performance of these candidates on modern and latest FPGA devices from Xilinx. This work serves as performance investigation of leading SHA-3 finalists on most up-to-date FPGAs.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.430-432
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• 2015

This paper describes a hardware implementation of ultra-lightweight block cipher algorithm PRESENT-80/128 that supports for two master key lengths of 80-bit and 128-bit. The PRESENT algorithm that is based on SPN (substitution and permutation network) consists of 31 round transformations. A round processing block of 64-bit data-path is used to process 31 rounds iteratively, and circuits for encryption and decryption are designed to share hardware resources. The PRESENT-80/128 crypto-processor designed in Verilog-HDL was verified using Virtex5 XC5VSX-95T FPGA and test system. The estimated throughput is about 550 Mbps with 275 MHz clock frequency.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.907-910
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• 1993

This paper describes the use of fuzzy control and decision making to simulate the control of traffic flow at an intersection. To show the value of fuzzy logic as an alternative method for control of traffic environments. A traffic environment includes the lanes to and from an intersection, the intersection, vehicle traffic, and signal lights in the intersection. To test the fuzzy logic controller, a computer simulation was constructed to model a traffic environment. A typical cross intersection was chosen for the traffic environment, and the performance of the fuzzy logic controller was compared with the performance of two different types of conventional control. In the hardware verifications, fuzzy logic was used to control acceleration of a model train on a circular path. For the software experiment, the fuzzy logic controller proved better than conventional control methods, especially in the case of highly uneven traffic flow between different directions. On the hardware si e of the research, the fuzzy acceleration control system showed a marked improvement in smoothness of ride over crisp control.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.485-487
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• 2017

The whirlpool hash function adopted as an ISO / IEC standard 10118-3 by the international standardization organization is an algorithm that provides message integrity based on an SPN (Substitution Permutation Network) structure similar to AES block cipher. In this paper, we describe the hardware implementation of the Whirlpool hash function. The round block is designed with a 64-bit data path and encryption is performed over 10 rounds. To minimize area, key expansion and encryption algorithms use the same hardware. The Whirlpool hash function was modeled using Verilog HDL, and simulation was performed with ModelSim to verify normal operation.

• Journal of Semiconductor Engineering
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• v.2 no.3
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• pp.136-141
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• 2021

This paper analyzes the tree expansion for multiple-input multiple-output (MIMO) detection in the viewpoint of hardware implementation. The tree expansion is to calculate path metrics of child nodes performed in every visit to a node while traversing the detection tree. Accordingly, the tree-expansion unit (TEU), which is responsible for such a task, has been an essential component in a MIMO detector. Despite the paramount importance, the analyses on the TEUs in the literature are not thorough enough. Accordingly, we further investigate the hardware complexity of the TEUs to suggest a guideline for selection. In this paper, we focus on a pair of major ways to implement the TEU: 1) a full parallel realization; 2) a transformation of the formulae followed by common subexpression elimination (CSE). For a logical comparison, the numbers of multipliers and adders are first enumerated. To evaluate them in a more practical manner, the TEUs are implemented in a 65-nm CMOS process, and their propagation delays, gate counts, and power consumptions were measured explicitly. Considering the target specification of a MIMO system and the implementation results comprehensively, one can choose which architecture to adopt in realizing a detector.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.799-802
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• 1998

As we know, gigabit ethernet is a new technology to be substituted for current fast ethernet used widely in local area network. The switch used in gigabit ethernet should deal with frames in giga-bps. To do such a fast switching, we need that serveral processes meet the budgets, such as MAC address table lookup, several giga speed path setup, fast scheduling, and etc. Especially MAC address table lookup has to be processed in the same speed with speed of incoming packets, thus the bottleneck in the process can cause packet loss by the overflow in the input buffer. We devise new practical hardware hashing method to perform fast table lookup by minimizing the number of external memory access and accelerating with hardware.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.34S no.1
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• pp.36-42
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• 1997

This paper proposes a high-speed contention resolution scheme featuring high flexibility to the bursty traffic for an input buffering ATM switching architecture and its hardware strategy. The scheme is based on the threshold on the occupancy of the input buffer. As the proposed scheme utilizes the threshold, it has high flexibility to the fluctuations of the input traffic. The hardware strategy for the proposed policy is provided with the aim of the simple structure that achieves the reduction of the signal path and the power consumption. The performance on the average buffer size of the proposed policy is performed and compared with the conventional schame under the bursty traffic through both the analysis based on the markov hain and the simulation. The relations among the parameters on the proposed policy is analyzed to improve the performance.