• Aerospace Engineering and Technology
• /
• v.11 no.1
• /
• pp.145-157
• /
• 2012

The novel limit cycle analysis of the attitude control system using jet thrusters was presented based on a phase plane method by paper. It was shown in the software simulation results that the analysed results of the limit cycle was more accurate than those of the Haloulakos' method. But it was not verified in the real system. The proposed method is verified in the reaction control system for KSLV-I via an real time hardware in the loop simulation. It can be shown in this test that analyzed result of the limit cycle is very accurate.

• Journal of IKEEE
• /
• v.12 no.2
• /
• pp.75-80
• /
• 2008

There are many researches to reduce power consumption of battery-operated Transceiver for 2.4 GHz smartRF applications. However, components such as processor, memory and LCD based power managements reach the limit of reducing power consumption. To overcome the limit, this research proposes novel low-power Transceiver and transceiver Hardware Design. Experimental results in the real smartRF Transceiver show that the proposed methods can reduce power consumption additionally than component based power managements.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.13 no.5
• /
• pp.2357-2380
• /
• 2019

In this paper, we investigate the impact of hardware impairments (HWIs) on the performance of a downlink massive MIMO system. We consider a single-cell system with maximum ratio transmission (MRT) as precoding scheme, and with all the HWIs characteristics such as phase noise, distortion noise, and amplified thermal noise. Based on the system model, we derive closed-form expressions for a typical user data rate under two scenarios: when a common local oscillator (CLO) is used at the base station and when separated oscillators (SLOs) are used. We also derive closed-form expressions for the downlink transmit power required for some desired per-user data rate under each scenario. Compared to the conventional system with ideal transceiver hardware, our results show that impairments of hardware make a finite upper limit on the user's downlink channel capacity; and as the number of base station antennas grows large, it is only the hardware impairments at the users that mainly limit the capacity. Our results also show that SLOs configuration provides higher data rate than CLO at the price of higher power consumption. An approach to minimize the effect of the hardware impairments on the system performance is also proposed in the paper. In our approach, we show that by reducing the cell size, the effect of accumulated phase noise during channel estimation time is minimized and hence the user capacity is increased, and the downlink transmit power is decreased.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.12 no.5
• /
• pp.95-105
• /
• 2002

This paper describes an efficient method to implement a hardware circuit of RSA public key cryptographic algorithm, which is important to public-key cryptographic system for an authentication, a key exchange and a digital signature. The RSA algorithm needs a modular exponential for its cryptographic operation, and the modular exponential operation is consists of repeated modular multiplication. In a numerous algorithm to compute a modular multiplication, the Montgomery algorithm is one of the most widely used algorithms for its conspicuous efficiency on hardware implementation. Over the past a few decades a considerable number of studies have been conducted on the efficient hardware design of modular multiplication for RSA cryptographic system. But many of those studies focused on the decrease of operating time for its higher performance. The most important thing to design a hardware circuit, which has a limit on a circuit area, is a trade off between a small circuit area and a feasible operating time. For these reasons, we modified the Montgomery algorithm for its efficient hardware structure for a system having a limit in its circuit area and implemented the refined algorithm in the IESA system developed for ETRI's smart card emulating system.

• 제어로봇시스템학회:학술대회논문집
• /
• 1996.10a
• /
• pp.77-82
• /
• 1996

This paper is concerned with how to utilize kinematic redundancy to reconstruct the inverse kinematic solution which is not attainable due to hardware limitations. By analyzing the error due to hardware limitations, we are to show that the recoverability of limitation reduces to the solvability of a reconstruction equation under the feasibility condition. It will be next shown that the reconstruction equation is solvable if the configuration is not a joint-limit singularity. The reconstruction method will be proposed based on the geometrical analysis of recoverability of hardware limitations. The method has the feature that no task motion error is induced by the hardware limitations while minimizing a possible null motion error, under the recoverability assumed.

• Proceedings of the KIEE Conference
• /
• 2003.04a
• /
• pp.435-437
• /
• 2003

Recently, as the road capacity reaches the limit and environmental problems becomes serious, there is gradually increased a need for railroad vehicles that are environment-friendly and have time regularity, reliability and safety. Accordingly, in addition to conventional railroad vehicles, lots of vehicles are being newly developed. We developed the hardware and software of the measurement system for on-line test and evaluation of korean hish speed train. The software controls the hardware of the measurement data and acts as interface between users and the system hardware. In this paper, we is studied for electric apparatus performance of railway vehicle using sensor. In order to this test is developed signal conversion system. Using this system, we obtained important result for pantograph voltage, battery voltage, axle speed, and running speed.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.16 no.12S
• /
• pp.1210-1216
• /
• 2003

Recently, as the road capacity reaches the limit and environmental problems becomes serious, there is gradually increased a need for railroad vehicles that are environment-friendly and have time regularity, reliability, and safety. Accordingly, in addition to conventional railroad vehicles, lots of vehicles are being newly developed. We developed the hardware and software of the measurement system for on-line test and evaluation of korean high speed train. The software controls the hardware of the measurement system and acts as interface between users and the system hardware. In this paper, practical experiment are performed to verify mechanical performance of motor and main transformer for Korean high speed rail. The experimental test carried out by using new temperature measurement method and verify the temperature performance of motor and transformer is verified.

• IEIE Transactions on Smart Processing and Computing
• /
• v.4 no.4
• /
• pp.237-250
• /
• 2015

This paper describes a hardware-oriented algorithm and its conceptual implementation in a real-time speed limit traffic sign detection system on an automotive-oriented field-programmable gate array (FPGA). It solves the training and color dependence problems found in other research, which saw reduced recognition accuracy under unlearned conditions when color has changed. The algorithm is applicable to various platforms, such as color or grayscale cameras, high-resolution (4K) or low-resolution (VGA) cameras, and high-end or low-end FPGAs. It is also robust under various conditions, such as daytime, night time, and on rainy nights, and is adaptable to various countries' speed limit traffic sign systems. The speed limit traffic sign candidates on each grayscale video frame are detected through two simple computational stages using global luminosity and local pixel direction. Pipeline implementation using results-sharing on overlap, application of a RAM-based shift register, and optimization of scan window sizes results in a small but high-performance implementation. The proposed system matches the processing speed requirement for a 60 fps system. The speed limit traffic sign recognition system achieves better than 98% accuracy in detection and recognition, even under difficult conditions such as rainy nights, and is implementable on the low-end, low-cost Xilinx Zynq automotive Z7020 FPGA.

• Proceedings of the KIEE Conference
• /
• 2002.11d
• /
• pp.197-199
• /
• 2002

The invention of VHDL(Very High Speed Integrated Circuit Hardware Description Language), Technical language of Hardware, is a kind of turning point in digital circuit designing, which is being more and more complicated and integrated. Because of its excellency in expression ability of hardware, VHDL is not only used in designing Hardware but also in simulation for verification, and in exchange and conservation, composition of the data of designs, and in many other ways. Especially, It is very important that VHDL is a Technical language of Hardware standardized by IEEE, intenational body with an authority. The biggest problem in modern circuit designing can be pointed out in two way. One is a problem how to process the rapidly being complicated circuit complexity. The other is minimizing the period of designing and manufacturing to survive in a cutthroat competition. To promote the use of VHDL, more than a simple use of simulation by VHDL, it is requested to use VHDL in composing logical circuit with chip manufacturing. And, by developing the quality of designing technique, it can contribute for development in domestic industry related to ASIC designing. In this paper in designing SMPS(Switching mode power supply), programming PWM by VHDL, it can print static voltage by the variable load, connect computer to chip with byteblaster, and download in Max(EPM7064SLCS4 - 5)chip of ALTER. To achieve this, it is supposed to use VHDL in modeling, simulating, compositing logic and product of the FPGA chip. Despite its limit in size and operating speed caused by the specific property of FPGA chip, it can be said that this method should be introduced more aggressively because of its prompt realization after designing.

• Journal of KIISE
• /
• v.42 no.2
• /
• pp.177-182
• /
• 2015

The era of multi-core processors has begun since the limit of the clock speed has been reached. These days, multi-core technology is used not only in desktops, servers, and table PCs, but also in smartphones. In this architecture, there is always interference between processes, because of the sharing of system resources. To address this problem, cache partitioning is used, which can be roughly divided into two types: software and hardware cache partitioning. When it comes to dynamic cache partitioning, hardware cache partitioning is superior to software cache partitioning, because it needs no page copy. In this paper, we compare the effectiveness of hardware and software cache partitioning on the AMD Opteron 6282 SE, which is the only commodity processor providing hardware cache partitioning, to see whether this technique can be effectively deployed in dynamic environments.