Browse > Article
http://dx.doi.org/10.5626/JOK.2015.42.2.177

Performance Comparison between Hardware & Software Cache Partitioning Techniques  

Park, JiWoong (Seoul National Univ.)
Yeom, HeonYoung (Seoul National Univ.)
Eom, Hyeonsang (Seoul National Univ.)
Publication Information
Journal of KIISE / v.42, no.2, 2015 , pp. 177-182 More about this Journal
Abstract
The era of multi-core processors has begun since the limit of the clock speed has been reached. These days, multi-core technology is used not only in desktops, servers, and table PCs, but also in smartphones. In this architecture, there is always interference between processes, because of the sharing of system resources. To address this problem, cache partitioning is used, which can be roughly divided into two types: software and hardware cache partitioning. When it comes to dynamic cache partitioning, hardware cache partitioning is superior to software cache partitioning, because it needs no page copy. In this paper, we compare the effectiveness of hardware and software cache partitioning on the AMD Opteron 6282 SE, which is the only commodity processor providing hardware cache partitioning, to see whether this technique can be effectively deployed in dynamic environments.
Keywords
multi-core processor; cache partitioning; page coloring; page copy overhead;
Citations & Related Records
연도 인용수 순위
  • Reference
1 Zhang, Xiao, Sandhya Dwarkadas, and Kai Shen, "Towards practical page coloring-based multicore cache management," Proc. of the 4th ACM European conference on Computer systems, pp. 89-102, 2009.
2 Advanced Micro Devices, BIOS and Kernel Developer's Guide (BKDG) for AMD Family 15h Models 00h-0Fh Processors. 2012.
3 Lin, Jiang, et al., "Gaining insights into multicore cache partitioning: Bridging the gap between simulation and real systems," High Performance Computer Architecture 2008 (HPCA 2008), pp. 367-378, 2008.
4 Cho, Sangyeun, and Lei Jin, "Managing distributed, shared L2 caches through OS-level page allocation," Proc. of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, pp. 455-468, 2006.
5 Tam, David, et al., "Managing shared L2 caches on multicore systems in software," Workshop on the Interaction between Operating Systems and Computer Architecture, pp. 26-33, 2007.
6 Soares, Livio, David Tam, and Michael Stumm, "Reducing the harmful effects of last-level cache polluters with an OS-level, software-only pollute buffer," Proc. of the 41st annual IEEE/ACM International Symposium on Microarchitecture, pp. 258-269, 2008.
7 Huang, Tao, et al., "Combining Process-Based Cache Partitioning and Pollute Region Isolation to Improve Shared Last Level Cache Utilization on Multicore Systems," Trust, Security and Privacy in Computing and Communications (TrustCom 2013), pp. 1153-1160, 2013.
8 Qureshi, Moinuddin K., and Yale N. Patt, "Utilitybased cache partitioning: A low-overhead, high-performance, runtime mechanism to partition shared caches," Proc. of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, pp. 423-432, 2006.
9 Rafique, Nauman, Won-Taek Lim, and Mithuna Thottethodi, "Architectural support for operating system-driven CMP cache management," Proc. of the 15th international conference on Parallel architectures and compilation techniques, pp. 2-12, 2006.
10 Cook, Henry, et al., "A hardware evaluation of cache partitioning to improve utilization and energyefficiency while preserving responsiveness," Proc. of the 40th Annual International Symposium on Computer Architecture, pp. 308-319, 2013.