• Journal of Multimedia Information System
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• v.5 no.4
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• pp.273-276
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• 2018

In video compression standards, the entropy coding is essential to the high performance compression because redundancy of data symbols is removed. Binary arithmetic coding is one of high performance entropy coding methods. However, the dependency between consecutive binary symbols prevents improving the throughput. For the throughput enhancement, a new probability model is proposed for encoding multi-symbols at one time. In the proposed method, multi-symbol encoder is implemented with only adders and shifters, and the multiplication table for interval subdivision of binary arithmetic coding is removed. Compared to the compression ratio of CABAC of H.264/AVC, the performance degradation on average is only 1.4% which is negligible.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.9
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• pp.1605-1614
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• 2008

This paper proposed a new VLSI architecture of motion estimation (ME) and compensation (MC) for efficient video compression and implemented it to hardware. ME is generally calculated using SAD result. So we proposed a new arithmetic method for SAD. The proposed SAD calculation method increases arithmetic efficiency and decreases external memory usage. Finally it increases performance of ME/MC. The proposed ME/MC hardware was implemented to ASIC with TSMC 90nm HVT CMOS library. The implemented hardware occupies about 330K gates and stably operates the clock frequency of 143MHz.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.41 no.1
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• pp.9-18
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• 2004

This paper presents an efficient image compression method for memory reduction in multimedia processor which can be simply implemented in hardware and provides high performance. The multimedia processor, which includes processing of high-resolution images and videos, requires large memories: they are external frame memories to store frames and internal line memories for implementing some linear filters. If we can reduce those memories by adopting a simple compression method in multimedia processor, it will strengthen its cost competitiveness. There exist many standards for efficiently compressing images and videos. However, those standards are too complex for our purpose and most of them are 2-D block-based methods, which do not support raster scanned input and output. In this paper, we propose a low-complexity compression method which has good performance, can be implemented with simple hardware logic, and supports raster scan. We have adopted 1${\times}$8 Hadamard transform for simple implementation in hardware and compression efficiency. After analyzing the coefficients, we applied an adaptive thresholding and quantization. We provide some simulation results to analyze its performance and compare with the existing methods. We also provide its hardware implementation results and discuss about cost reduction effects when applied in implementing a multimedia processor.

• Proceedings of the IEEK Conference
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• 2004.08c
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• pp.636-639
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• 2004

In present, there are many methods such as DCT, Wavelet Transform, or Quantization -to the image compression field, but the basic image compression method have based on DCT. The representative thing of the efficient techniques for information compression is DCT method. It is more superior than other information conversion method. It is widely applied in digital signal processing field and MPEG and JPEG which are selected as basis algorithm for an image compression by the international standardization group. It is general that DCT is consisted of using multiplier with main arithmetic blocks having many arithmetic amounts. But, the use of multiplier requires many areas when hardware is embodied, and there is fault that the processing speed is low. In this paper, we designed the hardware module that could run high-speed operation using row-column separation calculation method and Chen algorithm by distributed arithmetic method using ROM table instead of multiplier for design DCT module of high speed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.446-457
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• 2017

In order to reduce the size of frame memory or bus bandwidth, frame memory compression (FMC) recompresses reconstructed or reference frames of video codecs. This paper proposes a novel FMC design based on discrete wavelet transform (DWT) - set partitioning in hierarchical trees (SPIHT), which supports fine-scalable throughput and is area-efficient. In the proposed design, multi-cores with small block sizes are used in parallel instead of a single core with a large block size. In addition, an appropriate pipelining schedule is proposed. Compared to the previous design, the proposed design achieves the processing speed which is closer to the target system speed, and therefore it is more efficient in hardware utilization. In addition, a scheme in which two passes of SPIHT are merged into one pass called merged refinement pass (MRP) is proposed. As the number of shifters decreases and the bit-width of remained shifters is reduced, the size of SPIHT hardware significantly decreases. The proposed FMC encoder and decoder designs achieve the throughputs of 4,448 and 4,000 Mpixels/s, respectively, and their gate counts are 76.5K and 107.8K. When the proposed design is applied to high efficiency video codec (HEVC), it achieves 1.96% lower average BDBR and 0.05 dB higher average BDPSNR than the previous FMC design.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.4 no.1
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• pp.34-39
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• 2004

Huffman coding which has been used in many data compression algorithms is a popular data compression technique used to reduce statistical redundancy of a signal. It has been proposed that the Huffman algorithm can decode efficiently using characteristics of the Huffman tables and patterns of the Huffman codeword. We propose a new Huffman decoding algorithm which used a multi way tree search and present an efficient hardware implementation method. This algorithm has a small logic area and memory space and is optimized for high speed decoding. The proposed Huffman decoding algorithm can be applied for many multimedia systems such as MPEG audio decoder.

• Proceedings of the KOSOMBE Conference
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• v.1994 no.12
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• pp.92-95
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• 1994

As computer systems to make medical practice easy are widely used, a special hardware system processing medical data fast becomes more important. To meet the urgent demand for high speed image processing, especially image compression and decompression, we designed and implemented the medical image CODEC (COder/BECoder) based on MISD(Multiple Instruction Single Data stream) architecture to adopt parallelism in it. Considering not being a standart scheme of medical mage compression/decompress ion, the CODEC is designed programable and general. In this paper, we use JPEG (Joint Photographic Experts Group) algorithm to process images fast and evalutate it.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.1
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• pp.62-68
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• 2007

H.264 video compression in digital multimedia broadcasting (DMB) shows significantly high compression ratio over conventional algorithms, while its required hardware cost and power consumption are also $3{\sim}5$ times larger. Consequently, low-hardware-cost and low-power H.264 decoder SoC is essential for commercial digital multimedia broadcasting terminals. This paper describes low-power design and implementation of core blocks in H.264 decoder SoC.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.37 no.3
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• pp.79-85
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• 2000

In the communication technology, there is necessary data compression to transfer data more quickly and bigger amount in the same condition. And that should bring down the cost consequently. This paper shows that how to apply compression software and hardware to attain the issue that mentioned previous in data communication technology as well as, trying to find the solution for the system delay problem and to improve efficiency demanded to them. To achieve these purposes, 1 will study and analyze the efficiency of compression system to realize realtime data compression transfer system using LZS compression algorithm.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2022.11a
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• pp.112-115
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• 2022

The process of deep learning usually needs to deal with massive data which has greatly limited the development of deep learning technologies today. Convolutional Neural Network (CNN) structure is often used to solve image classification problems. However, a large number of images may be required in order to train an image in CNN, which is a heavy burden for existing computer systems to handle. If the image data can be compressed under the premise that the computer hardware system remains unchanged, it is possible to train more datasets in deep learning. However, image compression usually adopts the form of lossy compression, which will lose part of the image information. If the lost information is key information, it may affect learning performance. In this paper, we will analyze the effect of image compression on deep learning performance on CNN-based cat and dog classification. Through the experiment results, we conclude that the compression of images does not have a significant impact on the accuracy of deep learning.