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http://dx.doi.org/10.6109/jkiice.2008.12.9.1605

Design of High-Performance ME/MC IP for Video SoC  

Seo, Young-Ho (광운대학교 교양학부)
Choi, Hyun-Jun (광운대학교 전자재료공학과)
Kim, Dong-Wook (광운대학교 전자재료공학과)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.12, no.9, 2008 , pp. 1605-1614 More about this Journal
Abstract
This paper proposed a new VLSI architecture of motion estimation (ME) and compensation (MC) for efficient video compression and implemented it to hardware. ME is generally calculated using SAD result. So we proposed a new arithmetic method for SAD. The proposed SAD calculation method increases arithmetic efficiency and decreases external memory usage. Finally it increases performance of ME/MC. The proposed ME/MC hardware was implemented to ASIC with TSMC 90nm HVT CMOS library. The implemented hardware occupies about 330K gates and stably operates the clock frequency of 143MHz.
Keywords
motion estimation; compensation; video compression; VLSI; hardware design;
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