• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.8
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• pp.148-155
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• 2014

In this research a signal processing system is designed for detecting the ultrasonic signal envelope using Xilinx's Zynq SoC(system on chip). As a design tool, Vivado IDE(integrated design environment) is used to hierarchically design the whole signal processing system. The proposed system consists of a Zynq-internal ADC, an FIR(finite impulse response) BPF(band pass filter), an absolute value calculator, an FIR LPF(lpw pass filter), and the Kalman filter. Under this configuration, two design schemes, HW design scheme with LPF as a final stage and HW/SW co-design scheme with a Kalman filter as a final stage, are compared in terms of the performance and efficiency. As a result, envelope detecting performances of the two schemes are proved to be almost same, but the HW/SW co-design is verified to be much more efficient than the HW design considering the much smaller time consumption during system design.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.7
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• pp.1480-1483
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• 2009

In this paper, the hardware(HW) and software(SW) co-design methodology of H.264/AVC decoder using ARM-Excalibur is proposed. The SoC consists of embedded processor, memory, peripheral device and logic circuits. Recently, the co-design method which designs simultaneously HW and SW part is a new paradigm in SoC design. Because the optimization for partitioning the SoC system is very difficult, the verification must be performed earlier in design flow. We designed the H.264 and AVC Decoder using co-design method. It is shown that, for the proposed co-design method, the performance improvements can be obtained.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.24 no.4
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• pp.593-605
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• 2014

In this paper, we propose the efficient HW/SW co-design method of light-weight cryptography such as HIGHT, PRESENT and PRINTcipher using GEZEL. At first the symmetric cryptographic algorithms were designed using the GEZEL language which is efficiently used for HW/SW co-design. And for the improvement of performance the HW optimization theory such as unfolding, retiming and so forth were adapted to the cryptographic HW module conducted by FSMD. Also, the operation modes of those algorithms were implemented using C language in 8051 microprocessor, it can be compatible to various platforms. For providing reliable communication between HW/SW and preventing the time delay the improved handshake protocol was chosen for enhancing the performance of the connection between HW/SW. The improved protocol can process the communication-core and cryptography-core on the HW in parallel so that the messages can be transmitted to SW after HW operation and received from SW during encryption operation.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.117-120
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• 2001

This paper presents a HW/SW co-design environments and its validation for development of virtual component on the 32-bit RISC core which is used in the design of Information-Appliance-On-a-Chip. For the experimental environment, we developed the cycle-accurate instruction set simulator based on SE3208 RISC core of ADChips. To verify the function of RISC core at the cycle level, we implemented the verification environment by grafting this simulator on the Seamless CVE which is a commercial co-verification environment.

• Journal of the Institute of Convergence Signal Processing
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• v.10 no.4
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• pp.274-279
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• 2009

The flow of a universal system-level design methodology consists of system specification, system-level hardware/software partitioning, co-design, co-verification using virtual or physical prototype, and system integration. In this paper, verification environments based-on SystemVerilog and SystemC, one is native-code co-verification environment which makes prompt functional verification possible and another is SystemVerilog layered testbench which makes clock-level verification possible, are implemented. In native-code co-verification, HW and SW parts of SoC are respectively designed with SystemVerilog and SystemC after HW/SW partitioning using SystemC, then the functional interaction between HW and SW parts is carried out as one simulation process. SystemVerilog layered testbench is a verification environment including corner case test of DUT through the randomly generated test-vector. We adopt SystemC to design a component of verification environment which has multiple inheritance, and we combine SystemC design unit with the SystemVerilog layered testbench using SystemVerilog DPI and ModelSim macro. As multiple inheritance is useful for creating class types that combine the properties of two or more class types, the design of verification environment adopting SystemC in this paper can increase the code reusability.

• Journal of KIISE:Computing Practices and Letters
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• v.8 no.3
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• pp.261-267
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• 2002

In SOC(System On a Chip) designs, reducing time and cast for design verification is the most critical to improve the design productivity. this is mainly because the designs require co-verifying HW together with SW, which results in the increase of verification complexity drastically. In this paper, to cope with the verification crisis in SOC designs, we propose a new verification methodology, so called integrated co-verification, which lightly combine both co-simulation and co-emulation in unified and seamless way. We have applied our integrated co-verification to ARM/AMBA platform-based co-verification environment with a commercial co-verification tool, Seamless CVE, and a physical prototyping board. The experiments has shown clear advantage of the proposed technique over conventional ones.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.6
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• pp.93-99
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• 2017

In this research the TOF (time of flight) of ultrasonic signal is measured using Xilinx's Zynq SoC (system on chip). The TOF is calculated from the difference between periods during which RF (radio frequency) and ultrasonic signals come across a distance, and then travelling distance is obtained by multiplying the TOF by the ultrasonic speed in the air. For this purpose, a ultrasonic pulse is generated from a Zynq's internal ADC, a FIR (finite impulse response) filter, and a Kalman filter. And a RF reference pulse is generated from a RF interface. Based on baremetal multiprocessing, the Kalman filter and the RF interface are c-programmed on Zynq's dual processor cores, with other components fabricated on Zynq's FPGA. With this HW/SW co-design, both lower resource utilization and much smaller designing period were obtained than the HW design. As a design tool, Vivado IDE(integrated design environment) is used to design the whole signal processing system in hierarchical block diagrams.

• Journal of Convergence Society for SMB
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• v.3 no.1
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• pp.31-41
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• 2013

There have been various recent methods proposed in detecting driver drowsiness (DD) to avert fatal accidents. This work proposes a hardware/software (HW/SW) co-design approach in implementation of a DD detection system adapted from an AdaBoost-based object detection algorithm with Haar-like features [1] to monitor driver's eye closure rate. In this work, critical functions of the DD detection algorithm is accelerated through custom hardware components in order to speed up processing, while the software component implements the overall control and logical operations to achieve the complete functionality required of the DD detection algorithm. The HW/SW architecture was implemented on an Altera DE2 board with a video daughter board. Performance of the proposed implementation was evaluated and benchmarked against some recent works.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.641-642
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• 2011

This paper presents method of constructing the embedded systems based on hardware-software codesign which is the important fields of $21^{st}$ information technology. First, we describe the classification and necessity of embedded systems, and we discuss the consideration and classification for constructing the embedded systems. Also, we discuss the embedded systems modeling. The proposed embedded systems based on hardware-software co-design is important gradually, we expect that it involve the many IT fields in the future.

• Journal of the Korea Society of Computer and Information
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• v.15 no.9
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• pp.1-8
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• 2010

The key challenge in HW/SW co-design is how to choose the appropriate HW/SW partitioning from the vast array of possible options in the mapping set. In this paper we present a unique and efficient approach for addressing this problem known as Customized Heuristic Algorithm for Reducing Mapping Sets(CHARMS). CHARMS uses sensitivity to individual task computational complexity as well the computed weighted values of system performance influencing metrics to streamline the mapping sets and extract the most optimal cases. Using H.263 encoder, we show that CHARMS sieves out 95.17% of the sub-optimal mapping sets, leaving the designer with 4.83% of the best cases to select from for run-time implementation.