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HW/SW Co-design For an Ultrasonic Signal Processing System Using Zynq SoC

Zynq SoC를 이용한 초음파 신호처리 시스템 HW/SW co-design

  • Lim, Byung gyu (Department of Information and Communication Engineering, Sunmoon University) ;
  • Kang, Moon Ho (Department of Information and Communication Engineering, Sunmoon University)
  • 임병규 (선문대학교 정보통신공학과) ;
  • 강문호 (선문대학교 정보통신공학과)
  • Received : 2014.06.03
  • Accepted : 2014.07.29
  • Published : 2014.08.25

Abstract

In this research a signal processing system is designed for detecting the ultrasonic signal envelope using Xilinx's Zynq SoC(system on chip). As a design tool, Vivado IDE(integrated design environment) is used to hierarchically design the whole signal processing system. The proposed system consists of a Zynq-internal ADC, an FIR(finite impulse response) BPF(band pass filter), an absolute value calculator, an FIR LPF(lpw pass filter), and the Kalman filter. Under this configuration, two design schemes, HW design scheme with LPF as a final stage and HW/SW co-design scheme with a Kalman filter as a final stage, are compared in terms of the performance and efficiency. As a result, envelope detecting performances of the two schemes are proved to be almost same, but the HW/SW co-design is verified to be much more efficient than the HW design considering the much smaller time consumption during system design.

본 연구에서는 Xilinx의 Zynq SoC(system on chip)를 이용하여 초음파신호의 포락선을 검출하기 위한 신호처리 시스템을 설계하였다. 설계 툴로 Vivado IDE(integrated design environment)를 이용하여, 초음파 신호처리를 위한 전체 과정을 계층적 블록의 형태로 설계하였다. 제안된 시스템은 Zynq-7010의 내장 ADC, FIR(finite impulse response) 밴드패스 필터, 절대값 계산모듈, FIR 로우패스 필터 및 Kalman 필터 등으로 구성되며, 최종 단으로서 FIR 로우패스 필터를 사용하는 HW design 방식과 Kalman 필터를 사용하는 HW/SW co-design 방식에 대해 성능과 유효성을 비교하였다. 비교결과, 포락선 검출 성능에 있어서는 두 방식이 서로 유사한 특성을 갖지만, 시스템 개발에 소요되는 시간 측면에서는 HW/SW co-design 방식이 HW design 방식에 비해 훨씬 더 효율적임이 확인되었다.

Keywords

References

  1. "Zynq-7000 All Programmable SoC Overview," DS190 (v1.6) Xilinx, December 2, 2013.
  2. Fleming, S. T. and Thomas, D. B., "FPGA based control for real time systems," 23rd International Conference on Field Programmable Logic and Applications(FPL), pp. 1-2, 2013,
  3. Eberli, F., "Next Generation FPGAs and SOCs-How Embedded Systems Can Profit," IEEE Conference on Computer Vision and Pattern Recognition Workshops(CVPRW), pp. 610-613, 2013.
  4. Russell, M. and Fischaber, S., "OpenCV based road sign recognition on Zynq," 11th IEEE International Conference on Industrial Informatics (INDIN), pp. 596-601, 2013.
  5. Wehner, P., Ferger, M., Gohringer, D., and Hubner, M., "Rapid prototyping of a portable HW/SW co-design on the virtual zynq platform using SystemC," IEEE 26th International Conference on SOC(SOCC), pp. 296-300, 2013.
  6. Gilliland, S., Govindan, P., Gonnot, T., and Saniie, J., "Performance evaluation of FPGA based embedded ARM processor for ultrasonic imaging," IEEE International Ultrasonics Symposium (IUS), pp. 519-522, 2013.
  7. Bruckner, H. P., Spindeldreier, C., and Blume, H., "Energy-efficient inertial sensor fusion on heterogeneous FPGA-fabric/RISC System on Chip," Seventh International Conference on Sensing Technology (ICST), pp. 506-511, 2013.
  8. Astarloa, A., Lazaro, J., Bidarte, U., Zuloaga, A., and Idirin, M., "System-on-Chip implementation of Reliable Ethernet Networks nodes," 39th Annual Conference of the IEEE Industrial Electronics Society, IECON, pp. 2329-2334, 2013.
  9. J. Y., Cho and M. H., Kang, "Design of a Ultrasonic Oil Level Meter Using a FPGA," Journal of The Institute of Electronics Engineers of Korea, Vol. 49, no. 11, pp. 169-174, November 2012. https://doi.org/10.5573/ieek.2012.49.11.167
  10. Ramsey, F., "Understanding the Basis of the Kalman Filter Via a Simple and Intuitive Derivation," IEEE SIGNAL PROCESSING MAGAZINE, pp. 128-132, SEPTEMBER 2012.
  11. Vivado Design Suite User Guide, Using the Vivado IDE, Xilinx, Dec. 18, 2013.
  12. Vivado Design Suite User Guide, Designing with IP, Xilinx, May 1, 2014.
  13. Vivado Design Suite User Guide, Programming and Debugging, Xilinx, Apr. 2014.
  14. LogiCORE IP XADC Wizard v3.0 Product Guide for Vivado Design Suite, Oct. 2, 2013
  15. LogiCORE IP FIR Compiler v7.1 Product Guide for Vivado Design Suite, Dec. 18, 2013
  16. Signal Processing Toolbox For Use with MATLAB version 6, the MathWorks, 2013.

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