• Korean Journal of Materials Research
• /
• v.4 no.8
• /
• pp.921-926
• /
• 1994

The characteristics of gate oxide significantly depend on the last chemical solution used in cleaning process. The standard RCA, HF-last, SC1-last, and HF-only processes are the pre-gate oxide cleaning processes utilized in this experiment. Cleaning process was followed by thermal oxidation in oxidation furnace at $900^{\circ}C$. A 100$\AA$ gate oxide was grown and characterized with using lifetime detector, VPD AAS, SIMS, TEM, and AFM. The results of HF-last and HF-only were shown to be very effective to remove the metallic impurities. And these two splits also showed long minority carrier lifetimes. The surface and interface morphologies of the oxide were examined with AFM and TEM. The rough surface morphologies were observed with the cleaning splits containing the SC1 solution. The smooth surface and interface was observed with the HF-only cleaning process.

• Korean Chemical Engineering Research
• /
• v.45 no.2
• /
• pp.203-207
• /
• 2007

In this paper efficient method for particle removal from silicon wafers by usage of HF and ozone was studied. It was found that at least 0.3 vol% concentration of HF was required for particle removal and removal efficiency increased with the application of megasonic in ozonated water. Additional cleaning with minute amount of ammonia (0.01 vol%) after HF/Ozone step showed over 99% in removal efficiency. It is proposed that the superior cleaning efficiency of HF-Ozone-ammonia is due to micro-etching of silicon surface and impediment of particle re-adsorption in alkali environment. Compared to SC-1 cleaning method micro roughness has also been slightly improved. Therefore it is expected that HF-ozone-ammonia cleaning method is a viable alternative to the conventional wet cleaning methods.

• Bulletin of the Korean Chemical Society
• /
• v.18 no.7
• /
• pp.737-740
• /
• 1997

The influence of cyclic treatments with H2O2/DIW (1 : 10) and HF/DIW (1 : 100) on the roughness of silicon surface in the wet chemical processing was investigated by atomic force microscopy (AFM). During the step of the SC-1 cleaning, there is a large increase in roughness on the silicon surface which will result in the poor gate oxide breakdown properties. The roughness of the silicon wafer after the SC-1 cleaning step was reduced by cyclic treatments of hydrogen peroxide solution and hydrofluoric acid solution instead of HF-only cleaning. AFM images after each step clearly illustrated that the average roughness of silicon surface after three times treatments with H2O2 and HF solutions was reduced by 10 times compared with that after the SC-1 cleaning step.

• Journal of Surface Science and Engineering
• /
• v.30 no.6
• /
• pp.374-381
• /
• 1997

We have studied the effect of the interface between tungsten silicide and polysilicon the silicide reaction. The results showed that the cleaning of the silicon surface prior to the deposition of tungsten silicide affected the interface properties, thereby leading to the difference in the resistivity and surface morhpology of tungsten silicide. Compared with HF cleaning, the use of SCl cleaning yielded higher resistivity of tungsten silicide at the low anneal temperature (up to $900^{\circ}C$). However, furtherature to $1000^{\circ}C$ reduced the resistivity significantly, similar to that obtained with HF cleaning. It was also observed that the annealing of WSix/HF-cleaned poly-si allowed the formation of bucking weve (partially decohesion area) on the surface. In contrast, the use of SCl celaning did not produce the buckling waves on the surface. Also the presence of 200$\AA$ -thick TiW between tungsten silicide and HF-cleaned poly-Si effectively prevented the formation of the waves. However, high-temperature annealing of WSix/200A-TiW/Poly-Si allowed the excess silicon in tungsten silicide to precipitate inside the silcide, causing the slight increase of the resistivity after annealing at $1050^{\circ}C$.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.11 no.1
• /
• pp.33-40
• /
• 1998

The composite SiO$_2$/Si$_3$N$_4$/SiO$_2$(ONO) film formed by oxidation on nitride film has been widely studied as DRAM stacked capacitor multi-dielectric films. Load lock(L/L) LPCVD system by HF cleaning is used to improve electrical capacitance and to scale down of effective thickness for memory device, but is brings a new problem. Nitride film deposited using HF cleaning shows selective deposition on poly silicon and oxide regions of capacitor. This problem is avoidable by carpeting chemical oxide using $H_2O$$_2$cleaning before nitride deposition. In this paper, we study the limit of nitride thickness for abnormal oxidation and the initial deposition time for nitride deposition dependent on underlayer materials. We proposed an advanced fabrication process for stacked capacitor in order to avoid selective deposition problem and show the usefulness of nitride deposition using L/L LPCVD system by $H_2O$$_2$cleaning. The natural oxide thickness on polysilicon monitor after HF and $H_2O$$_2$cleaning are measured 3~4$\AA$, respectively. Two substrate materials have the different initial nitride deposition times. The initial deposition time for polysilicon is nearly zero, but initial deposition time for oxide is about 60seconds. However the deposition rate is constant after initial deposition time. The limit of nitride thickness for abnormal oxidation under the HF and $H_2O$$_2$cleaning method are 60$\AA$, 48$\AA$, respectively. The results obtained in this study are useful for developing ultra thin nitride fabrication of ONO scaling and for avoiding abnormal oxidation in stacked capacitor application.

• Korean Journal of Materials Research
• /
• v.6 no.4
• /
• pp.395-400
• /
• 1996

반도체 소자가 점점 고집적회되고 고성능화되면서 Si 기판 세정 방법은 그 중요성이 더욱 더 커지고 있다. 특히 ULSI급 소자에서는 세정 방법이 소자 생산수율 및 신뢰성에 큰 영향을 끼치고 있다. 본 연구에서는 HF-last 세정에 UV/O3과 SC-1 세정을 삽입하여 그 영향을 관찰하였다. 세정 방법은 HF-last 세정을 기본으로 split 1(piranha+HF), split 2(piranha+UV/O3+HF), split 3(piraha+SC-1+HF), split 4(piranha+(UV/O3+HF) x3회 반복)의 4가지 세정 방법으로 나누어 실험하였다. 세정을 마친 Si 기판은 Total X-Ray Fluorescence Spectroscopy(AFM)을 사용하여 표면거칠기를 측정하였다. 또한 세정류량을 측정하고, Atomic Force Microscopy(AFM)을 사용하여 표면거칠기를 측정하였다. 또한 세정후 250$\AA$의 gate 산화막을 성장시켜 전기적 특성을 측정하였다. UV/O3을 삽입한 split 2와 split 4세정방법이 물리적, 전기적 특성에서 우수한 특성을 나타냈고, SC-1을 삽입한 split 3세정 방법이 표준세정인 split 1세정 방법보다 우수하지 못한 결과를 나타냈다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.16 no.7
• /
• pp.569-572
• /
• 2003

In this study, we evaluated the dilute HF cleaning to reduce residual defects made by metal CMP process. The purpose of this test is to observe the existence of barrier metal damage during DHF cleaning on condition that it should not affect metal thin film reliability, so we will get rid of slurry residual particles as a main defect of the metal CMP process for the better yield. In-line defect data showed us that slurry residual particles were removed by DHF application. The HF rinse significantly reduced metal contamination levels and surface roughness. The best effect by additional oxide loss was discovered when Dilute HF condition is 10".

• Journal of the Korean Chemical Society
• /
• v.47 no.6
• /
• pp.608-613
• /
• 2003

In order to remove particles on surface of post-oxide CMP wafer, new cleaning solution was prepared by mixing with DHF (Diluted HF), nonionic surfactant PAAE (Polyoxyethylene Alkyl Aryl Ether), DMSO (Dimethylsulfoxide) and D.I.W.. Silicone wafers were intentionally contaminated by silica, alumina and PSL (polystylene latex) which had different zeta potentials in cleaning solution. This cleaning solution under megasonic irradiation could remove particles and metals simultaneously at room temperature in contrast to traditional AMP (mixture of $NH_4OH,\;H_2O_2$ and D.I.W) without any side effects such as increasing of microroughness, metal line corrosion and deposition of organic contaminants. This suggests that this cleaning solution would be useful future application with copper CMP in brush cleaning process as well as traditional post CMP cleaning process.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2006.11a
• /
• pp.366-367
• /
• 2006

In general, HF chemistry lifts off the particles during scrubbing after polishing and effectively removes particles. It is sometimes impossible to apply HF chemistry on W plug due to the degradation of electrical characteristics of a device. In this paper, a post W CMP cleaning process is proposed to remove residue particles without applying HF chemistry. After W CMP, recessed plugs are created, therefore they easily trap slurry particles during CMP process. These particles in recessed plug are not easy to remove by brush scrubbing when $NH_4OH$ chemistry is used for the cleaning because the brush surface can not reach the recessed area of plugs. Buffing with oxide slurry was followed by W CMP due to its high selectivity to W. The buffing polishes only oxide slightly which creates higher plug profiles than surrounding oxide. Higher profiles make the brush contact much more effectively and result in a similar particle removal efficiency even in $NH_4OH$ cleaning to that in HF brush scrubbing.

• Journal of the Semiconductor & Display Technology
• /
• v.10 no.3
• /
• pp.15-19
• /
• 2011

The performance of the DRAM is strongly dependent on the purity and surface roughness of the TIT (TiN/Insulator/ TiN) capacitor electrodes. Hence, in the present study, we evaluate the effects of organic contamination and change of surface roughness on the cylindrical TIT capacitor electrodes during the wet cleaning process by various analytical techniques such as TDMS, AFM, XRD and V-SEM. Once the sacrificial oxide and PR (Photo Resist) are removed by HF, the organic contamination and surface oxide films on the bottom Ti/TiN electrode become visible. With prolonged HF process, the surface roughness of the electrode is increased, whereas the amount of oxidized Ti/TiN is reduced due to the HF chemicals. In the 80nm DRAM device fabrication, the organic contamination of the cylindrical TIT capacitor may cause defects like SBD (Storage node Bridge Defect). The SBD fail bit portion is increased as the surface roughness is increased by HF chemicals reactions.