• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.135-138
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• 2005

HDL(Hardware Description Language) is the most important modem tools used to describe hardware, and becomes important as we move to higher levels of abstraction. The HDL has been made brisk use of in analog design, MEMS device[1-2], process related field as well as digital design. The most important characteristics of HDL is Abstraction which is the strongest tool that extend greatly designer's design ability. In this paper by the Modelling Continuum with hierarchical structure of abstraction, we apply UML(Unified Modeling Language) to SoC Design with HDL UML makes an easy and visual description of the various levels of abstraction, and gives designers good flexible modeling capabilty for SoC Design.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.190-195
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• 2005

The hearing aid chip described in this paper is an analog & digital mixed system. The design focuses on the$\mu$DSP core. This $\mu$DSP core includes internal time delays to two inputs from front and rear microphones. The paper consists of two parts; one is the composure and signal processing algorithm of digital hearing aids and the other is Verilog HDL codes for$\mu$DSP cores. All digital modules in the design were coded and synthesized by Verilog HDL codes which were verified by Mentor Graphics and Synopsis semiconductor chip design tools.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.05a
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• pp.757-759
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• 2013

Until just a few years ago, digital circuit design techniques in register transfer level using Verilog or VHDL have been recognized as the up-to-date way compared with the traditional schematic design, and truly they have been used as the most popular skill for most chip designs. However, with the advent of era in which the complexity of semiconductor chip counts over billion transistors with advanced manufacturing technology, designing in register transfer level became too complex to meet the requirements of the needs, so the design paradigm has to change so that both design and synthesis can be done in higher level of abstraction. Bluespec SystemVerilog (BSV) is the only HDL which enables both circuit design and generating synthesizable code in the system level developed so far. In this contribution, I survey and analyze the features which supports the new paradigm in the BSV HDL, not very familiar to industry yet.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.801-804
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• 2005

In this paper, we designed an 8-bit color adjustor for SDTV using Verilog HDL. The conversion block requires a lot of multiplication. So we adopted Booth algorithm to reduce amount of operation and processing time. To improve speed, we designed the system output as parallel structure. We synthesized the designed system using Xilinx ISE and verified the operation through simulation using Modelsim.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.68-73
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• 2006

This, paper proposes a cosimulation methodology that results in an efficient SoC design as well as fast verification by integrating HDL, SystemC, and algorithm-level abstraction using the design tools Active-HDL and Matlab's Simulink. To demonstrate the proposed design methodology, we implemented the design technique on a serial connection multi-channel speaker system. We have demonstrated the proposed cosimulation method utilizing an ARM processor based SoC Master board with the AMBA bus interface and a Xilinx Vertex4 FPGA. The proposed method has the advantage of simultaneous simulation verification of both software and hardware parts in high levels of abstraction mixed with some performance critical parts in more concrete RTL codes. This allows relatively fast and easy design of a speaker connection system which typically requires significant amount of data processing for verification.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1744-1747
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• 2002

In late years, the tendency to shift the design language of electronic circuits from HDL to C-based languages of C/C)1 and so on is strengthened. The current of adopting these software languages thrives by necessity to solve the problem peculiar to HDL that verification of design is difficult. When we use C-based languages, we can describe the design by higher abstraction degree, mount the design as both hardware and software finally and so that express the design part which is not made clear at early stage the same one language. Therefore, the flexibility of design very improves, the design work in environment the range of applying the whole systems become possible. This paper introduces example at having applied C-based languages in image processing LSI design and describes that the design technique of C-based languages is effective for the system design.

• Journal of IKEEE
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• v.26 no.4
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• pp.577-583
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• 2022

Verilog-HDL-based modeling can be performed to confirm the fast operation characteristics after setting the design parameters of each block considering the stability of the system by performing linear phase-domain modeling on the phase-locked loop. This paper proposed Verilog-HDL modeling including DCO noise and DTC nonlinear characteristic. After completing the modeling, the time-domain transient simulation can be performed to check the feasibility and the functionality of the proposed PLL system, then the phase noise result from the system design based on the functional model can be verified comparing with the ideal phase noise graph. As a result of the comparison of simulation time (6 us), the Verilog-HDL-based modeling method (1.43 second) showed 484 times faster than the analog transistor level design (692 second) implemented by TSMC 0.18-㎛.

• ETRI Journal
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• v.33 no.5
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• pp.731-740
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• 2011

Reconfigurable computing using a field-programmable gate-array (FPGA) device has become a promising solution in system design because of its power efficiency and design flexibility. To bring the benefit of FPGA to many application programmers, there has been intensive research about automatic translation from high-level programming languages (HLL) such as C and C++ into hardware. However, the large gap of syntaxes and semantics between hardware and software programming makes the translation challenging. In this paper, we introduce a new approach for the translation by using the widely used GCC compiler. By simply adding a hardware description language (HDL) backend to the existing state-of- the-art compiler, we could minimize an effort to implement the translator while supporting full features of HLL in the HLL-to-HDL translation and providing high performance. Our translator, called GCC2Verilog, was implemented as the GCC's cross compiler targeting at FPGAs instead of microprocessor architectures. Our experiment shows that we could achieve a speedup of up to 34 times and 17 times on average with 4-port memory over PICO microprocessor execution in selected EEMBC benchmarks.

• ETRI Journal
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• v.35 no.3
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• pp.480-490
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• 2013

As technology evolves into the deep submicron level, synchronous circuit designs based on a single global clock have incurred problems in such areas as timing closure and power consumption. An asynchronous circuit design methodology is one of the strong candidates to solve such problems. To verify the feasibility and efficiency of a large-scale asynchronous circuit, we design a fully clockless 32-bit processor. We model the processor using an asynchronous HDL and synthesize it using a tool specialized for asynchronous circuits with a top-down design approach. In this paper, two microarchitectures, basic and enhanced, are explored. The results from a pre-layout simulation utilizing 0.13-${\mu}m$ CMOS technology show that the performance and power consumption of the enhanced microarchitecture are respectively improved by 109% and 30% with respect to the basic architecture. Furthermore, the measured power efficiency is about 238 ${\mu}W$/MHz and is comparable to that of a synchronous counterpart.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.67 no.1
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• pp.9-14
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• 2018

In this paper, we introduce an AES-based security chip for the embedded system of Internet of Things(IoT). We used Verilog HDL to implement the AES algorithm in FPGA. The designed AES module creates 128-bit cipher by encrypting 128-bit plain text and vice versa. RTL simulations are performed to verify the AES function and the theory is compared to the results. An FPGA emulation was also performed with 40 types of test sequences using two Altera DE0-Nano-SoC boards. To evaluate the performance of security algorithms, we compared them with AES implemented by software. The processing cycle per data unit of hardware implementation is 3.9 to 7.7 times faster than software implementation. However, there is a possibility that the processing speed grow slower due to the feature of the hardware design. This can be solved by using a pipelined scheme that divides the propagation delay time or by using an ASIC design method. In addition to the AES algorithm designed in this paper, various algorithms such as IPSec can be implemented in hardware. If hardware IP design is set in advance, future IoT applications will be able to improve security strength without time difficulties.