• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.05a
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• pp.757-759
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• 2013

Until just a few years ago, digital circuit design techniques in register transfer level using Verilog or VHDL have been recognized as the up-to-date way compared with the traditional schematic design, and truly they have been used as the most popular skill for most chip designs. However, with the advent of era in which the complexity of semiconductor chip counts over billion transistors with advanced manufacturing technology, designing in register transfer level became too complex to meet the requirements of the needs, so the design paradigm has to change so that both design and synthesis can be done in higher level of abstraction. Bluespec SystemVerilog (BSV) is the only HDL which enables both circuit design and generating synthesizable code in the system level developed so far. In this contribution, I survey and analyze the features which supports the new paradigm in the BSV HDL, not very familiar to industry yet.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.7
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• pp.1653-1659
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• 2013

In this paper, we propose a new ECAD software for efficiently analyzing and debugging of digital architecture implemented in Verilog HDL or VHDL codes. This software firstly elaborates HDL codes so as to extract internal architecture structure, then generates several graphical aids such as hierarchical schematics by applying placement and routing algorithm, object tree to show configuration of each module, instance tree to show hierarchical structure of instances, and SPD (Signal Propagation Diagram) to show internal interconnections. It is more important function that same objects in different views(HDL codes, object tree, instance tree, SPD, waveform etc.) can be highlighted at the starting any object. These functions are sure to improve efficiency of manual job to fix bugs or to analyze HDL codes.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2000.12a
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• pp.241-244
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• 2000

In this paper we designed a simple 8-bit processor using HDL. The simple 13-bit processor has 19 instructions with three different addressing modes. The processor includes registers - IR, PC, SP, Y, MA, MD, AC, IN, OUT - and 256Kbyte memory. We examined the operation of the processor through simulation and then synthesized it on FPGA.

• KIPS Transactions on Computer and Communication Systems
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• v.3 no.3
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• pp.73-80
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• 2014

In this paper, we propose an incremental simulation method in event-driven HDL simulation to reduce the simulation execution time. In general, the simulation is repeated with a series of design changes. Incremental simulation is an efficient simulation method that shortens the simulation execution time for the following simulation by using the result of previous simulation. We have observed the effectiveness of the proposed approach through the experimentation with multiple real designs.

• Journal of the Korea Society of Computer and Information
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• v.7 no.4
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• pp.89-93
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• 2002

This paper describes an ALU core which is suitable for 32-bit DSP This ALU operates in 32-bit data and occupies the third stage, execution, among 5 stage pipeline structure. The supplied functions of the ALU are arithmetic operations, logical operations, shifting, and so on. For the implementation of this ALU core, each functional block is described by HDL. And the functional verification of the ALU core is performed through HDL simulation. This ALU is designed to use the 32-bit DSP.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.135-138
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• 2005

HDL(Hardware Description Language) is the most important modem tools used to describe hardware, and becomes important as we move to higher levels of abstraction. The HDL has been made brisk use of in analog design, MEMS device[1-2], process related field as well as digital design. The most important characteristics of HDL is Abstraction which is the strongest tool that extend greatly designer's design ability. In this paper by the Modelling Continuum with hierarchical structure of abstraction, we apply UML(Unified Modeling Language) to SoC Design with HDL UML makes an easy and visual description of the various levels of abstraction, and gives designers good flexible modeling capabilty for SoC Design.

• Journal of Internet Computing and Services
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• v.18 no.5
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• pp.1-8
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• 2017

Lightweight Encryption Algorithm(LEA) was developed by National Security Research Institute(NSRI) in 2013 and targeted to be suitable for environments for big data processing, cloud service, and mobile. LEA specifies the 128-bit message block size and 128-, 192-, and 256-bit key sizes. In this paper, block cipher LEA algorithm which can encrypt and decrypt 128-bit messages is designed using Verilog-HDL. The designed IP for encryption and decryption has a maximum throughput of 874Mbps in 128-bit key mode and that of 749Mbps in 192 and 656Mbps in 256-bit key modes on Xilinx Vertex5. The cryptographic IP of this paper is applicable as security module of the mobile areas such as smart card, internet banking, e-commerce and IoT.

• Journal of IKEEE
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• v.26 no.4
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• pp.577-583
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• 2022

Verilog-HDL-based modeling can be performed to confirm the fast operation characteristics after setting the design parameters of each block considering the stability of the system by performing linear phase-domain modeling on the phase-locked loop. This paper proposed Verilog-HDL modeling including DCO noise and DTC nonlinear characteristic. After completing the modeling, the time-domain transient simulation can be performed to check the feasibility and the functionality of the proposed PLL system, then the phase noise result from the system design based on the functional model can be verified comparing with the ideal phase noise graph. As a result of the comparison of simulation time (6 us), the Verilog-HDL-based modeling method (1.43 second) showed 484 times faster than the analog transistor level design (692 second) implemented by TSMC 0.18-㎛.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.8
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• pp.1735-1740
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• 2005

SoC design integrates many IPs that operate at different frequencies and the use of the different clock for each IP makes the design the most effective one. An asynchronous FIFO is required as a kind of a buffer to connect IPs that are asynchronous. However, in many cases, asynchronous FIFO is designed improperly and the cost of the wrong design is high. In this paper, an asynchronous FIFO is designed to transfer data across asynchronous clock domains by using a valid bit scheme that eliminates the problem of the metastability and synchronization altogether. This FIFO architecture is described in HDL and synthesized to the Bate level to compare with other FIFO scheme. The subject mater of this paper is under patent pending.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.05a
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• pp.390-393
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• 2003

In this paper, we study on an implementation of cell scheduler which arbitrates the ATM exchange efficiently and swiftly. The designed ATM cell scheduler of this paper is based on iSLIP scheduling algorithm. It is aimed at the high-speed implementation. The implemented cell scheduler approximately provides 100% throughput for cell scheduling. We present a basic structure for cell scheduler and describe by using the HDL and perform behavior level and timing simulation. The cell scheduler of this paper is designed to support 8-port switch fabric and can expand in 32-port switch fabric. The cell scheduler for supporting the 8-port switch fabric is designed in 2-stage pipelines for the grant and accept stages respectively.