[KSCI] Korea Science Citation Index Service

Design of an Asynchronous FIFO for SoC Designs Using a Valid Bit Scheme

Lee Yong-hwan (금오공과대학교 전자공학부)

Publication Information

Journal of the Korea Institute of Information and Communication Engineering / v.9, no.8, 2005 , pp. 1735-1740 More about this Journal

Abstract

SoC design integrates many IPs that operate at different frequencies and the use of the different clock for each IP makes the design the most effective one. An asynchronous FIFO is required as a kind of a buffer to connect IPs that are asynchronous. However, in many cases, asynchronous FIFO is designed improperly and the cost of the wrong design is high. In this paper, an asynchronous FIFO is designed to transfer data across asynchronous clock domains by using a valid bit scheme that eliminates the problem of the metastability and synchronization altogether. This FIFO architecture is described in HDL and synthesized to the Bate level to compare with other FIFO scheme. The subject mater of this paper is under patent pending.

Keywords

SoC; HDL; clock scheme;

Citations & Related Records

Reference

1	Clifford Cummings, Peter Alfke, 'Simulation and Synthesis Techniques for Asynchronous FIFO Design with Asynchronous Pointer Comparisons', SNUG San Jose paper, 2002
2	Clifford Cummings, 'Simulation and Synthesis Techniques for Asynchronous FIFO Design', SNUG San Jose paper 2002
3	Edward Paluch, 'Synthesis Optimized Universal Synchronous/Asynchronous Generic FIFO Design', SNUG San Jose 2003 paper

KSCI

Design of an Asynchronous FIFO for SoC Designs Using a Valid Bit Scheme SoC 설계를 위한 유효 비트 방식의 비동기 FIFO설계

Design of an Asynchronous FIFO for SoC Designs Using a Valid Bit Scheme