• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.11
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• pp.900-904
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• 2011

In this paper, we investigated an anomalous hump phenomenon under the positive bias stress in p-type LTPS TFTs. The devices with inferior electrical performance also show larger hump phenomenon. which can be explained by the sub-channel induced from trapped electrons under thinner gate oxide region. We can confirm that the devices with larger hump have larger interface trap density ($D_{it}$) and grain boundary trap density ($N_{trap}$) extracted by low-high frequency capacitance method and Levinson-Proano method, respectively. From the C-V with I-V transfer characteristics, the trapped electrons causing hump seem to be generated particularly from the S/D and gate overlapped region. Based on these analysis, the major cause of an anomalous hump phenomenon under the positive bias stress in p-type poly-Si TFTs is explained by the GIDL occurring in the S/D and gate overlapped region and the traps existing in the channel edge region where the gate oxide becomes thinner, which can be inferred by the fact that the magnitude of the hump is dependent on the average trap densities.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.05a
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• pp.450-453
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• 1999

In this paper, The relationship between device performance and channel length(1.5-50$\mu$m) in polysilicon thin-film transistors fabricated by SPC technology was Investigated by measuring electric Properties such as 1-V characteristics, field effect mobility, threshold voltage, subthreshold swing, and trap density in grain boundary with channel length. The drain current at ON-state increases with decreasing channel length due to increase of the drain field, while OFF-state current (leakage current) is independent of channel length. The field effect mobility decrease with channel length due to decreasing carrier life time by the avalanche injection of the carrier at high drain field. The threshold voltage and subthreshold swing decrease with channel length, and then increase in 1.5 $\mu$m increase of increase of trap density in grain boundary by impact ionization.

• Korean Journal of Materials Research
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• v.2 no.1
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• pp.12-18
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• 1992

The trap levels of ZnO-based varistor are obtained by Isothermal Capacitance Transient Spectroscopy method. Here ICTS measuring system consists of YHP 4192A Impedance Analyzer and a personal computer for the data acquisition. Between $-40^{\circ}C$ and $60^{\circ}C$, the grain boundary trap levels of 0.48 and 0.94eV were detected for $ZnO-Bi_2O_3-MnO$ system. The hole omission spectra are observed in the case of the addition of CoO into the $ZnO-Bi_2O_3$ system, while the electron emission spectra are detected in the case of the addition of MnO. The nonlinear resistance coefficient $\alpha$ increases with the decrease of the dormer concentration. Finally, the trap level density of $ZnO-Bi_2O_3-MnO$ system is found to decrease with the amount of CoO, while $\alpha$ is found to increase with the amount of CoO.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.4
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• pp.106-111
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• 1996

Schottky diodes are fabricated on laser annealed and unannealed polysilicon substrate and their electrical characteristics are studied and analyzed. Current of laser annealed devices are larger than that of unannealed devices because of grain growth, decrease of grain boundary and trap density, lowering of grain boundary barrier height, decrease of dopant segregation. At low forward bias (<0.7V), currents of unanealed devices are larger. Soft breakdown voltages of laser annealed devices are larger than that of unannealed devices.

• Electrical & Electronic Materials
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• v.5 no.3
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• pp.310-319
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• 1992

LPCVD 방법으로 625.deg.C와 560.deg.에서 증착한 다결정 실리콘에 As이온주입량을 lx$10^{13}$-lx$10^{16}$/$cm^{2}$로 변화시키면서 열처리 전, 후의 미세구조와 전기적 특성 변화를 조사하였다. 625.deg.C에서 증착한 시편은 columnar구조를 하고 있어 표면이 매우 거칠었으며 900.deg.C, 30분 열처리 후에는 As doping 농도에 관계없이 결정립 크기는 200-300.angs.정도였다. 560.deg.C에서 증착한 시편은 비정질 상태로열처리 후에는 1000.angs.이상의 큰 결정립을 갖는 타원형의 결정립으로 성장하였으며 표면이 매우 smooth하였다. 같은 doping 농도에서 전기 전도도와 Hall mobility는 비정질 상태로 증착한 시편이 큰 결정립으로 인하여 다결정 상태로 증착한 시편에 비해 크게 되었다. Grain boundary trapping model에 의해 계산한 potential barrier height는 As doping 농도가 증가함에 따라 감소하였으며 grain boundary trap density는 증착 온도, As doping 농도 및 결정립 크기에 크게 관계없이 3.6~5*$10^{12}$/$cm^{2}$로 측정되었다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.3
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• pp.197-202
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• 2008

In this paper, we proposed an analytical model for TFT which has series of the polycrystalline structures. An average speed is defined as carrier speed by the electric field. The effective square is suggested as the area of grain without depletion for the changed grain size. First, physical parameters such as grain size, channel lenght and trap density, have been changed to prove the validity of the average speed model and the value of the effective square has been estimated through drain-source current.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.40 no.6
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• pp.582-589
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• 1991

We used Cd Se as the semiconductor to analyze the Poly-TFT. Cd Se TFT is fabricated by the vacuum evaporation method and the characteristics curves of the current-voltage are obtained using the results of measurement of Cd Se TFT devices. Employing least square method and Rosenbrock algorithm, we can extract the device parameters(grain boundary mobility, trap density). The current-voltage relations calculated by extracted parameters are in good agreement with experimental results.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.2
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• pp.85-90
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• 2012

In this paper, we compared and analyzed 3D silicon-oxide-nitride-oxide-silicon (SONOS) multi layer flash memory devices fabricated on nitride or oxide layer, respectively. The device fabricated on nitride layer has inferior electrical properties than that fabricated on oxide layer. However, the device on nitride layer has faster program / erase speed (P/E speed) than that on the oxide layer, although having inferior electrical performance. Afterwards, to find out the reason why the device on nitride has faster P/E speed, 1/f noise analysis of both devices is investigated. From gate bias dependance, both devices follow the mobility fluctuation model which results from the lattice scattering and defects in the channel layer. In addition, the device on nitride with better memory characteristics has higher normalized drain current noise power spectral density ($S_{ID}/I^2_D$>), which means that it has more traps and defects in the channel layer. The apparent hooge's noise parameter (${\alpha}_{app}$) to represent the grain boundary trap density and the height of grain boundary potential barrier is considered. The device on nitride has higher ${\alpha}_{app}$ values, which can be explained due to more grain boundary traps. Therefore, the reason why the devices on nitride and oxide have a different P/E speed can be explained due to the trapping/de-trapping of free carriers into more grain boundary trap sites in channel layer.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.12
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• pp.969-976
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• 2011

In this study we aims to evaluate the effects of 1/3 mol% $Co_3O_4$ addition on the reaction, microstructure development, resultant electrical properties, and especially the bulk trap and grain boundary properties of $ZnO-Bi_2O_3-Sb_2O_3$ (Sb/Bi=2.0, 1.0, and 0.5) system (ZBS). The samples were prepared by conventional ceramic process, and characterized by XRD, density, SEM, I-V, impedance and modulus spectroscopy (IS & MS) measurement. In addition of $Co_3O_4$ in $ZnO-Bi_2O_3-Sb_2O_3$ (ZBSCo), the phase development, density, and microstructure were controlled by Sb/Bi ratio. Pyrochlore on cooling was reproduced in all systems. The more homogeneous microstructure was obtained in ZBSCo (Sb/Bi=1.0) system. In ZBSCo, the varistor characteristics were improved drastically (non-linear coefficient ${\alpha}$=23~50) compared to ZBS. Doping of $Co_3O_4$ to ZBS seemed to form $V^{\cdot}_o$(0.33 eV) as dominant defect. From IS & MS, especially the grain boundary of Sb/Bi=0.5 system is composed of electrically single barrier (0.93 eV) and somewhat sensitive to ambient oxygen with temperature.

• Proceedings of the KIEE Conference
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• 1989.11a
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• pp.83-86
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• 1989

Electrical conductivity, I - V and DLTS have been measured on polycrystalline samples of $\alpha-Fe_{2}O_{3}$ containing small deviation from stoichiometry and small amounts of added titanium. DLTS (Deep Level Transient Spectroscopy) in the current transient mode has been applied to the measurement of the trap density at the grain boundary. Titanium enters the $\alpha-Fe_{2}O_{3}$ lattice substitutionally as $Ti^{4+}$, thus producing an $Fe^{2+}$ and maintaining the average charge per cation at three. The $Fe^{2+}$acts as a donor center with respect to the surrounding $Fe^{3+}$ions.