• 한국전기전자재료학회논문지
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• 제16권9호
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• pp.765-770
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• 2003

We have developed a low-temperature, and low-pressure radical induced oxidation (RIO) technology, so that high-quality ultrathin silicon dioxide layers have been effectively produced with a high reproducibility, and successfully employed to realize high performace SiGe heterostructure complementary MOSFETs (HCMOS) lot the first time. The obtained oxide layer showed comparable leakage and breakdown properties to conventional furnace gate oxides, and no hysteresis was observed during high-frequency capacitance-voltage characterization. Strained SiGe HCMOS transistors with a 2.5 nm-thick gate oxide layer grown by this method exhibited excellent device properties. These suggest that the present technique is particularly suitable for HCMOS devices requiring a fast and high-precision gate oxidation process with a low thermal budget.

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권2호
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• pp.106-113
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• 2006

Electrical properties of $Si_{0.88}Ge_{0.12}(C)$ p-MOSFETs have been exploited in an effort to investigate $Si_{0.88}Ge_{0.12}(C)$ channel structures designed especially to suppress diffusion of dopants during epitaxial growth and subsequent fabrication processes. The incorporation of 0.1 percent of carbon in $Si_{0.88}Ge_{0.12}$ channel layer could accomodate stress due to lattice mismatch and adjust bandgap energy slightly, but resulted in deteriorated current-voltage properties in a broad range of operation conditions with depressed gain, high subthreshold current level and many weak breakdown electric field in gateoxide. $Si_{0.88}Ge_{0.12}(C)$ channel structures with boron delta-doping represented increased conductance and feasible use of modulation doped device of $Si_{0.88}Ge_{0.12}(C)$ heterostructures.

• 한국전기전자재료학회논문지
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• 제17권12호
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• pp.1301-1307
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• 2004

Reduced pressure chemical vapor deposition(RPCYD) technology has been investigated for the growth of SiGe epitaxial films with two dimensional in-situ doped boron impurities. The two dimensional $\delta$-doped impurities can supply high mobility carriers into the channel of SiGe heterostructure MOSFETs(HMOS). Process parameters including substrate temperature, flow rate of dopant gas, and structure of epitaxial layers presented significant influence on the shape of two dimensional dopant distribution. Weak bonds of germanium hydrides could promote high incorporation efficiency of boron atoms on film surface. Meanwhile the negligible diffusion coefficient in SiGe prohibits the dispersion of boron atoms: that is, very sharp, well defined two-dimensional doping could be obtained within a few atomic layers. Peak concentration and full-width-at-half-maximum of boron profiles in SiGe could be achieved in the range of 10$^{18}$ -10$^{20}$ cm$^{-3}$ and below 5 nm, respectively. These experimental results suggest that the present method is particularly suitable for HMOS devices requiring a high-precision channel for superior performance in terms of operation speed and noise levels to the present conventional CMOS technology.

• EDISON SW 활용 경진대회 논문집
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• 제3회(2014년)
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• pp.457-458
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• 2014

In this paper, quantum mechanical simulations of the double-gate ultra-thin body (DG-UTB) MOSFETs are performed according to the International Technology Roadmap of Semiconductors (ITRS) specifications planned for 2020, to devise the way for on-current ($I_{on}$) improvement. We have employed non-equilibrium Green's function (NEGF) approach and solved the self-consistent equations based on the parabolic effective mass theory [1]. Our study shows that the [100]/<001> Ge and GaSb channel devices have higher $I_{on}$ than Si channel devices under the body thickness ($T_{bd}$) <5nm condition.

• 대한전자공학회논문지SD
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• 제42권9호
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• pp.9-18
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• 2005

60 nm C-MOSFET 기술 분기점 이상의 고성능, 저전력 트랜지스터를 구현 시키기 위해 SiGe/SiO2/Si위에 성장된 strained Si의 두께가 전자 이동도에 미치는 영향을 두 가지 관점에서 조사 연구하였다. 첫째, inter-valley phonon 산란 모델의 매개변수들을 최적화하였고 둘째, strained Si 반전층의 2-fold와 4-fold의 전자상태, 에너지 밴드 다이어그램, 전자 점유도, 전자농도, phonon 산란율과 phonon-limited 전자이동도를 이론적으로 계산하였다. SGOI n-MOSFET의 전자이동도는 고찰된 SOI 구조의 Si 두께 모든 영역에서 일반적인 SOI n-MOSFET보다 $1.5\~1.7$배가 높음이 관찰 되었다. 이러한 경향은 실험 결과와 상당히 일치한다. 특히 strained Si의 두께가 10 nm 이하일 때 Si 채널 두께가 6 nm 보다 작은 SGOI n-MOSFET에서의 phonon-limited 전자 이동도는 일반 SOI n-MOSFET과 크게 달랐다. 우리는 이러한 차이가 전자들이 suained SGOI n-MOSFET의 반전층에서 SiGe층으로 터널링 했기 때문이고, 반면에 일반 SOI n-MOSFET에서는 캐리어 confinement 현상이 발생했기 때문인 것으로 해석하였다. 또한 우리는 10 nm와 3 nm 사이의 Si 두께에서는 SGOI n-MOSFET의 phonon-limited 전자 이동도가 inter-valley phonon 산란율에 영향을 받는 다는 것을 확인하였으며, 이러한 결과는 더욱 높은 드레인 전류를 얻기 위해서 15 nm 미만의 채널길이를 가진 완전공핍 C-MOSFET는 stained Si SGOI 구조로 제작하여야 함을 확인 했다