• 한국전기전자재료학회논문지
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• 제16권7호
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• pp.573-578
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• 2003

Low temperature selective epitaxial growth of Si and SiGe has been obtained using an industrial single wafer chemical vapor deposition module operating at reduced pressure. Epitaxial Si and heteroepitaxial SiGe deposition with Ge content about 20 % has been studied as extrinsic base for self-aligned heterojunction bipolar transistors(HBTs), which helps to reduce the parasitic resistance to obtain higher maximum oscillation frequencies(f$\_$max/). The dependence of Si and SiGe deposition rates on exposed windows and their evolution with the addition of HCl to the gas mixture are investigated. SiH$_2$Cl$_2$ was used as the source of Si SEG(Selective Epitaxial Growth) and GeH$_4$ was added to grow SiGe SEG. The addition of HCl into the gas mixture allows increasing an incubation time even low growth temperature of 675∼725$^{\circ}C$. In addition, the selectivity is enhanced for the SiGe alloy and it was proposed that the incubation time for the polycrystalline deposit on the oxide is increased probably due to GeO formation. On the other hand, when only SiGe SEG(Selective Epitaxial Growth) layer is used for extrinsic base, it shows a higher sheet resistance with Ti-silicide because of Ge segregation to the interface, but in case of Si or Si/SiGe SEG layer, the sheet resistance is decreased up to 70 %.

• 한국진공학회지
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• 제7권2호
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• pp.77-81
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• 1998

RHEED(Reflection High Energy Electron Diffraction)상(pattern)의 거울반사점 (specular spot) 강도의 주기적인 진동을 이용하여, 계면금속(surfactant)Sn을 흡착하지 않은 경우와 흡착한 경우 Ge(111)표면 위에서 Ge의 층상성장을 조사하였다. 계면금속을 흡착하지 않았을 경우, 기판온도 $200^{\circ}C$에서 반점의 강도가 24ML정도 안정되게 진동하는 것으로 보 아, Ge층상성장의 최적온도로 생각되었다. 계면금속(Sn) 0.5ML를 Ge(111) 표면위에 흡착시 킨 후, Ge성장에서는 기판온도 $200^{\circ}C$에서 성장초기에 불규칙한 진동이 나타났으며, 반점강 도의 주기적인 운동이 흡착하지 않은 경우 보다 더 큰 진폭으로 38ML이상까지 관찰되었으 며 Ge이 성장하는 동안 d2$\times$2 구조의 변화가 없었다. 이는 계면금속이 교환작용으로 성장표 면 쪽으로 편석(segregation)하면서 흡착원자의 표면확산 거리를 저해시켜 3차원적 핵성장 에 의한 층상성장을 저해하고 대신 2차원적 성장을 도우는 것으로 생각된다.

• 한국전기전자재료학회논문지
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• 제22권11호
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• pp.905-909
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• 2009

The new Junction Field Effect Transistors (JFETs) with Silicon-germanium (SiGe) layers is investigated. This structure uses SiGe layer to prevent out diffusion of boron in the channel region. In this paper, we report electrical properties of SiGe JFET measured under various design parameters influencing the performance of the device. Simulation results show that out diffusion of boron is reduced by the insertion SiGe layers. Because the SiGe layer acts as a barrier to prevent the spread of boron. This proposed JFET, regardless of changes in fabrication processes, accurate and stable cutoff voltage can be controlled. It is easy to maintain certain electrical characteristics to improve the yield of JFET devices.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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• pp.297.1-297.1
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• 2014

칼코겐화합물은 주기율표 6족에서 산소를 제외한 칼코겐 원소가 하나 이상 포함되는 화합물 반도체 소재로 상변화 및 광전변환 특성을 가지고 있다. 이와 같은 칼코겐화합물의 장점을 이용하여 집적회로의 로직 블록 간의 신호 전달을 제어하는 프로그래머블 스위치를 구현 할 수 있다. 본 연구에서는 프로그래머블 스위치에 적용 가능한 칼코겐화합물로 널리 알려진 GeSbTe 및 GeTe 박막의 도핑에 따른 전기적, 구조적 특성 변화를 보고한다. RF magnetron sputtering 방식을 이용하여 doped GST 및 doped GeTe 박막을 증착하고 도핑에 따른 전기적, 구조적 특성을 관찰하였다. GST 박막의 경우 도핑에 의해 면저항 값이 증가하고 결정화 온도가 상승하는 것을 확인하였다. 반면 GeTe 박막에서는 도핑에 의해 면저항 값이 감소하고 결정화 온도가 낮아지는 것을 확인하였다. 이러한 결과로부터 GeSbTe 및 GeTe 박막의 전기적 특성은 도핑에 따라 변화하며, 도핑 조건을 적절히 조절함으로써 프로그래머블 스위치에 적용 가능한 칼코겐화합물의 확보가 가능하다는 결론을 내릴 수 있다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2000년도 하계학술대회 논문집 C
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• pp.1803-1805
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• 2000

This paper analyzes the effects of Ge profiles shape of SiGe heterojunction bipolar transistors (HBT's) for high frequency application. Device simulations using ATLAS/BLAZE for the SiGe HBT with trapezoidal or triangular Ge profile are carried out to optimize the device performance. An HBT with 15% triangular Ge profile shows higher cut-off frequency and DC current gain than that with 19% trapezoidal Ge profile. The cut-off frequency and BC gain are increased from 42GHz to 84GHz and from 200 to 600, respectively.

• 한국세라믹학회지
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• 제54권3호
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• pp.249-256
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• 2017

We design Ge-Al multilayer assemblies as anode materials for Li-ion batteries, in which Ge and Al thin films are alternately deposited by a radio sputtering method. By sandwiching Ge layers between Al layer, the cyclability, rate capability, and capacity of Ge are improved significantly. The success of the Ge-Al multilayer is attributed to the Al films. To maintain the integrity of electrical contact, Al acts as an elastic layer, which can expand or shrink with the Ge film upon lithiation or delithiation. In addition, the presence of the Al film on the surface can prevent direct contact of Ge and electrolyte, thereby reducing the growth of a SEI layer. Importantly, with high electrical and ionic conductivities, the Al film provides efficient electrical and ionic routes for electrons and Li-ions to access the Ge film, promoting a high specific capacity and high rate capability for Ge.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 하계학술대회 논문집 Vol.6
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• pp.21-22
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• 2005

Partially-depleted Silicon on insulator metal-oxide-semiconductor field- effect transistors (PD-SOI MOSFETs) with Silicon-germanium (SiGe) layer is investigated. This structure uses SiGe layer to reduce the kink effect in the floating body region near the bottom channel/buried oxide interface. Among many design parameters influencing the performance of the device, Ge composition is presented most predominant effects, simulation results show that kink effect is reduced with increase the Ge composition. Because the bandgap of SiGe layer is reduced at higher Ge composition, the hole current between body and SiGe layer is enhanced.

• 대한전자공학회논문지
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• 제26권11호
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• pp.1672-1678
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• 1989

Major problems preventing the device-quality GaAs/Si heterostructure are the lattice mismatch of about 4% and difference in thermal expansion coefficient by a factor of 2.64 between Si and GaAs. Ge is a good candidate for the buffer layer because its lattice parameter and thermal expansion coefficient are almost the same as those of GaAs. As a first step toward developing heterostructure such as GaAs/Ge/Si entirely by a home-built PAE (plasma-assisted epitaxy), Ge films have been deposited on p-type Si (100)substrate by the plasma assisted evaporation of solid Ge source. The characteristics of these Ge/Si heterostructure were determined by X-ray diffraction, SEM and Auge electron spectroscope. PAE system has been successfully applied to quality-good Ge layer on Si substrate at relatively low temperature. Furthermore, this system can remove the native oxide(SiO2) on Si substrate with in-situ cleaning procedure. Ge layer grown on Si substrate by PAE at substrate temperature of 450\ulcorner in hydrogen partial pressure of 10mTorr was expected with a good buffer layer for GaAs/Ge/Si heterostructure.

• Bulletin of the Korean Chemical Society
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• 제26권10호
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• pp.1543-1548
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• 2005

Two isostructural new alkaline earth germanium nitrides, $Sr_6Ge_5N_2\;and\;Ba_6Ge_5N_2$, were obtained as single crystals from constituent elements in molten Na. They both crystallize in space group $P_{mmn}$ (No. 59) with a = 4.0007(8), b = 17.954(3), c = 9.089(2) $\AA$, Z = 2, and a = 4.1620(2), b = 18.841(1), c = 9.6116(5) $\AA$, Z = 2, for $Sr_6Ge_5N_2\;and\;Ba_6Ge_5N_2$, respectively. Their crystal structure contains features for both Zintl and nitride phases: zigzag anionic chain of $_{\infty}Ge^{2-}$, and dumbbell-shaped bent anion of ${GeN_2}^{4-}$. Counter cations of Sr or Ba wrap these anionic units in a channel-like arrangement. Unlike in other germanium nitrides, bond lengths of both Ge-N arms of the ${GeN_2}^{4-}$, are same in $Sr_6Ge_5N_2\;and\;Ba_6Ge_5N_2$.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제43회 하계 정기 학술대회 초록집
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• pp.376-376
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• 2012

Semiconductor nanowires (NWs) are future building block for nano-scale devices. Especially, Ge NWs are fascinated material due to the high electrical conductivity with high carrier mobility. It is strong candidate material for post-CMOS technology. However, thermal stability of Ge NWs are poor than conventional semiconductor material such as Si. Especially, when it reduced size as small as nano-scale it will be melted around CMOS process temperature due to the melting point depression. Recently, Graphene have been intensively interested since it has high carrier mobility with single atomic thickness. In addition, it is chemically very stable due to the $sp^2$ hybridization. Graphene films shows good protecting layer for oxidation resistance and corrosion resistance of metal surface using its chemical properties. Recently, we successfully demonstrated CVD growth of monolayer graphene using Ge catalyst. Using our growth method, we synthesized Ge/graphene core/shell (Ge@G) NW and conducted it for highly thermal stability required devices. We confirm the existence of graphene shell and morphology of NWs using SEM, TEM and Raman spectra. SEM and TEM images clearly show very thin graphene shell. We annealed NWs in vacuum at high temperature. Our results indicated that surface melting phenomena of Ge NWs due to the high surface energy from curvature of NWs start around $550^{\circ}C$ which is $270^{\circ}C$ lower than bulk melting point. When we increases annealing temperature, tip of Ge NWs start to make sphere shape in order to reduce its surface energy. On the contrary, Ge@G NWs prevent surface melting of Ge NWs and no Ge spheres generated. Furthermore, we fabricated filed emission devices using pure Ge NWs and Ge@G NWs. Compare with pure Ge NWs, graphene protected Ge NWs show enhancement of reliability. This growth approach serves a thermal stability enhancement of semiconductor NWs.