• Proceedings of the KIPE Conference
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• 2002.07a
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• pp.707-710
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• 2002

A 120kV/70A high voltage switch has been installed at Korea Atomic Energy Research Institute in Taejon to supply power with Korea Superconducting Tokamak Advanced Research (KSTAR) Neutral Beam Injection (NBI) system. NBI system requires fast cutoff of the power supply voltage for protection of the grid when arc detected and fast turn-on the voltage for sustaining the beam current. Therefore the high voltage switch and arc current detection circuit are important part of the NBI power supply and there are much need for high voltage solid state switches in NBI system and a broad area of applications. This switch consisted of 100 series connected MOSFETs and adopted the proposed simple and reliable gate drive circuit without bias supply, Various results taken during the commissioning phase with a 100kW resistive load and NBI source are shown. This paper presents the detailed design of 120kV/70A high voltage MOSFETs switch and simple gate drive circuit. Problems with the high voltage switch and gate driver and solutions are also presented.

• Journal of Power Electronics
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• v.16 no.2
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• pp.786-797
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• 2016

This paper describes the design and development of a novel semiconductor-based solid-state switch for damped oscillating voltage test system. The proposed switch is configured as two identical series-connected switch stacks, each of which comprising 10 series-connected IGBT function units. Each unit consists of one IGBT, a gate driver, and an auxiliary voltage sharing circuit. A single switch stack can block 20 kV-rated high voltage, and two stacks in series are proven applicable to 30 kV-rated high voltage. The turn-on speed of the switch is approximately 250 ns. A flyback topology-based power supply system with a front-end power factor correction is built for the drive circuit by loosely inductively coupling each unit with a ferrite core to the primary side of a power generator to obtain the advantages of galvanic isolation and compact size. After the simulation, measurement, and estimation of the parasitic effect on the gate driver, a prototype is assembled and tested under different operating regimes. Experimental results are presented to demonstrate the performance of the developed prototype.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.1301-1304
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• 2008

In this study, we used a multiple phase scheme for the clock in the dual-pull-down driver for TFT display panels. In this scheme, the turn-on time for the transistors in the dual-pull-down structure was reduced from 1/2 to 1/4 or 1/8 of the period cycle time. While keeping proper operation of the transistor size of circuit was fine tuned to achieve an optimal performance. The relation between the active time and the transistor dimensions was obtained for the optimal design.

• Journal of Information Display
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• v.12 no.1
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• pp.61-67
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• 2011

A single-clock-driven shift register and a two-stage buffer are proposed, using p-type, low-temperature polycrystalline silicon thin-film transistors. To eliminate the clock skew problems and to reduce the burden of the interface, only one clock signal was adopted to the shift register circuit, without additional reference voltages. A two-stage, p-type buffer was proposed to drive the gate line load and shows a full-swing output without threshold voltage loss. The shift register and buffer were designed for the 3.31" WVGA ($800{\times}480$) LCD panel, and the fabricated circuits were verified via simulations and measurements.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.1251-1254
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• 2006

A novel a-Si TFT integrated gate driver circuit using multi-thread driving has been developed. The circuit consists of two independent shift registers alternating between the two mode, "wake" and "sleep". The degradation of the circuit is retarded since the bias stress is removed during the sleep mode. It has been successfully integrated in 14.1-in. XGA LCD Panel, showing enhanced stability.

• Journal of Power Electronics
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• v.13 no.4
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• pp.729-736
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• 2013

Knowledge of a power semiconductor's operating temperature is important in circuit design and converter control. Designing appropriate circuitry that does not affect regular circuit operation during virtual junction temperature measurement at actual operating conditions is a demanding task for engineers. The proposed method enables virtual junction temperature estimation with a dedicated modified gate driver circuit based on real-time measurement of a semiconductor's quasi-threshold voltage. A simulation was conducted before the circuit was designed to verify the concept and to determine the basic properties and potential drawbacks of the proposed method.

• Proceedings of the KIPE Conference
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• 2016.11a
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• pp.226-227
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• 2016

본 논문은 SiC Mosfet Gate Driver에서 Overcurrent상황 발생시 Mosfet 양단의 전압을 검출함으로써 스위칭 소자를 보호하는 Desaturation detction circuit에 대해 다룬다. IGBT와 다르게 SiC Mosfet의 경우 ohmic 영역과 saturation영역의 구분이 명확하지 않기 때문에 과전류 발생시 Mosfet 양단 전압을 검출하는데 어려움이 있다. 따라서 이를 보완하기 위하여 Mosfet drain측에 새로운 회로를 추가로 설계함으로써 이를 보완하여 효과적으로 양단전압을 검출한다.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.657-658
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• 2006

A Novel level-shifter circuit for Display Panel Driver is presented. A Proposed level-shifter is for the high speed and high-voltage driving capability. In order to achieve this purpose, the proposed level-shifter restricts and separates the Vgs of the output driver's pull-up PMOS and pull-down NMOS with Zener diode. And a speed-up PMOS transistor is introduced to reduce delay. The control signal of speed-up PMOS was designed by bootstrapping method to minimize the gate to source (Vgs) voltage to avoid Vgs breakdown.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.12
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• pp.31-38
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• 2010

This paper presents the design of a graphic memory for QVGA-scale LCD Driver IC (LDI). The graphic memory is designed based on the pseudo-SHAM for the purpose of small area, and the memory cell structure is designed using a bit line partitioning method to improve sensing characteristics and drivabilties in the line-read operation. Also, a collision protection circuit using C-gate is designed to control collisions between read/write operations and self-refresh/line-read operations effectively. The graphic memory circuit has been designed in transistor level using $0.18{\mu}m$ CMOS technology library and the operations of the graphic memory have been verified using Hspice. The results show that the bit-bitb line voltage difference, ${\Delta}V$ increases by 40%, the charge sharing time between bit and bitb voltages $T_{CHGSH}$ decreases by 30%, and the current during line-read decreases by 40%.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.805-808
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• 2005

In this study, the design of advanced LVDS(Low Voltage Differential Signaling) I/O interface circuit with new structural low triggering ESD(Electro-Static Discharge) protection circuit was investigated. Due to the differential transmission technique and low power consumption at same time. maximum transmission data ratio of designed LVDS transmitter was simulated to 5Gbps, Also, the LIGCSCR(Latch-up Immune Gate Coupled SCR)was designed. It consists of PLVTSCR (P-type Low Voltage Trigger SCR), control NMOS and RC network. The triggering voltage was simulated to 3.6V. And the latch-up characteristics were improved. Finally, we performed the layout high speed I/O interlace circuit with the low triggered ESD protection device in one-chip.