• Title/Summary/Keyword: Gate resistance

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Optimal Design of Trench Power MOSFET for Mobile Application

  • Kang, Ey Goo
    • Transactions on Electrical and Electronic Materials
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    • v.18 no.4
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    • pp.195-198
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    • 2017
  • This research analyzed the electrical characteristics of an 80 V optimal trench power MOSFET (metal oxide field effect transistor) for mobile applications. The power MOSFET is a fast switching device in fields with low voltage(<100 V) such as mobile application. Moreover, the power MOSFET is a major carrier device that is not minor carrier accumulation when the device is turned off. We performed process and device simulation using TCAD tools such as MEDICI and TSUPREM. The electrical characteristics of the proposed trench gate power MOSFET such as breakdown voltage and on resistance were compared with those of the conventional power MOSFET. Consequently, we obtained breakdown voltage of 100 V and low on resistance of $130m{\Omega}$. The proposed power MOSFET will be used as a switch in batteries of mobile phones and note books.

Temperature-Dependent Instabilities of DC characteristics in AlGaN/GaN-on-Si Heterojunction Field Effect Transistors

  • Keum, Dong-Min;Choi, Shinhyuk;Kang, Youngjin;Lee, Jae-Gil;Cha, Ho-Young;Kim, Hyungtak
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.14 no.5
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    • pp.682-687
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    • 2014
  • We have performed reverse gate bias stress tests on AlGaN/GaN-on-Si Heterostructure FETs (HFETs). The shift of threshold voltage ($V_{th}$) and the reduction of on-current were observed from the stressed devices. These changes of the device parameters were not permanent. We investigated the temporary behavior of the stressed devices by analyzing the temperature dependence of the instabilities and TCAD simulation. As the baseline temperature of the electrical stress tests increased, the changes of the $V_{th}$ and the on-current were decreased. The on-current reduction was caused by the positive shift of the $V_{th}$ and the increased resistance of the gate-to-source and the gate-to-drain access region. Our experimental results suggest that electron-trapping effect into the shallow traps in devices is the main cause of observed instabilities.

A Gate-Leakage Insensitive 0.7-V 233-nW ECG Amplifier using Non-Feedback PMOS Pseudo-Resistors in 0.13-μm N-well CMOS

  • Um, Ji-Yong;Sim, Jae-Yoon;Park, Hong-June
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.10 no.4
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    • pp.309-315
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    • 2010
  • A fully-differential low-voltage low-power electrocardiogram (ECG) amplifier by using the nonfeedback PMOS pseudo-resistors is proposed. It consists of two operational-transconductance amplifiers (OTA) in series (a preamplifier and a variable-gain amplifier). To make it insensitive to the gate leakage current of the OTA input transistor, the feedback pseudo-resistor of the conventional ECG amplifier is moved to input branch between the OP amp summing node and the DC reference voltage. Also, an OTA circuit with a Gm boosting block without reducing the output resistance (Ro) is proposed to maximize the OTA DC gain. The measurements shows the frequency bandwidth from 7 Hz to 480 Hz, the midband gain programmable from 48.7 dB to 59.5 dB, the total harmonic distortion (THD) less than 1.21% with a full voltage swing, and the power consumption of 233 nW in a 0.13 ${\mu}m$ CMOS process at the supply voltage of 0.7 V.

The effect of 3-mercapto-5-nitro-benzimidazole (MNB) and poly (methyl methacrylate) (PMMA) treatment sequence organic thin film transistor

  • Park, Jin-Seong;Suh, Min-Chul;Jeong, Jong-Han;Kim, Su-Young;Mo, Yeon-Gon
    • 한국정보디스플레이학회:학술대회논문집
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    • 2006.08a
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    • pp.1174-1177
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    • 2006
  • A bottom contact organic thin film transistor (OTFT) is fabricated with an organic double-layered gate insulator (GI) and pentacene. The PMMA and MNB layers are treated on gate insulator and source/drain (S/D, Au) before depositing pentacene to investigate device properties and pentacene growth. The sequence of surface treatment affects a device performance seriously. The ultra-thin PMMA (below 50A) was deposited on organic gate insulator and S/D metal by spin coating method, which showed no deterioration of on-state current (Ion) although bottom contact structure was exploited. We proposed that the reason of no contact resistance (Rc) increase may be due to a wettability difference in between PMMA / Au and PMMA / organic GI. As a result, the device treated by $PMMA\;{\rightarrow}\;MNB$ showed much better Ion behavior than those fabricated by $MNB\;{\rightarrow}\;PMMA$. We will report the important physical and electrical performance difference associated with surface treatment sequence.

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Decrease of Parasitic Capacitance for Improvement of RF Performance of Multi-finger MOSFETs in 90-nm CMOS Technology

  • Jang, Seong-Yong;Kwon, Sung-Kyu;Shin, Jong-Kwan;Yu, Jae-Nam;Oh, Sun-Ho;Jeong, Jin-Woong;Song, Hyeong-Sub;Kim, Choul-Young;Lee, Ga-Won;Lee, Hi-Deok
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.15 no.2
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    • pp.312-317
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    • 2015
  • In this paper, the RF characteristics of multi-finger MOSFETs were improved by decreasing the parasitic capacitance in spite of increased gate resistance in a 90-nm CMOS technology. Two types of device structures were designed to compare the parasitic capacitance in the gate-to-source ($C_{gs}$) and gate-to-drain ($C_{gd}$) configurations. The radio frequency (RF) performance of multi-finger MOSFETs, such as cut-off frequency ($f_T$) and maximum-oscillation frequency ($f_{max}$) improved by approximately 10% by reducing the parasitic capacitance about 8.2% while maintaining the DC performance.

DC and RF Characteristics of $0.15{\mu}m$ Power Metamorphic HEMTs

  • Shim, Jae-Yeob;Yoon, Hyung-Sup;Kang, Dong-Min;Hong, Ju-Yeon;Lee, Kyung-Ho
    • ETRI Journal
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    • v.27 no.6
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    • pp.685-690
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    • 2005
  • DC and RF characteristics of $0.15{\mu}m$ GaAs power metamorphic high electron mobility transistors (MHEMT) have been investigated. The $0.15{\mu}m{\times}100{\mu}m$ MHEMT device shows a drain saturation current of 480 mA/mm, an extrinsic transconductance of 830 mS/mm, and a threshold voltage of -0.65 V. Uniformities of the threshold voltage and the maximum extrinsic transconductance across a 4-inch wafer were 8.3% and 5.1%, respectively. The obtained cut-off frequency and maximum frequency of oscillation are 141 GHz and 243 GHz, respectively. The $8{\times}50{\mu}m$ MHEMT device shows 33.2% power-added efficiency, an 18.1 dB power gain, and a 28.2 mW output power. A very low minimum noise figure of 0.79 dB and an associated gain of 10.56 dB at 26 GHz are obtained for the power MHEMT with an indium content of 53% in the InGaAs channel. This excellent noise characteristic is attributed to the drastic reduction of gate resistance by the T-shaped gate with a wide head and improved device performance. This power MHEMT technology can be used toward 77 GHz band applications.

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Performance Enhancement due to Oxygen Plasma Treatment on the Gate Dielectrics of OTFTs (게이트 절연막의 $O_2$플라즈마 처리에 의한 펜타센 OTFT의 성능 개선)

  • 이명원;김광현;허영헌;안정근
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.40 no.7
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    • pp.494-498
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    • 2003
  • In this paper, the plasma treatment on gate surface has been applied prior to deposition of pentacene and the effects on performance were investigated. The Plasma treatment produced the mobility of 0.05$\textrm{cm}^2$/V.sec which is 10 times larger than the non-treated. The resistance was also reduced from 400K$\Omega$ to 50K$\Omega$. In addition, the standard deviation of performance parameters variation was reduced with the plasma exposure time, which implies that plasma treatment makes the gate surface states be uniform across the whole wafer area. The performance parameters were increased with the exposure time up to 5min, after which they degraded again. Therefore, the optimal exposure time was found to be 5min.

Characteristics of Ta-Ti alloy Metal for NMOS Gate Electrodes (NMOS 게이트 전극에 사용될 Ta-Ti 합금의 특성)

  • Kang, Young-Sub;Lee, Chung-Keun;Kim, Jae-Young;Hong, Shin-Nam
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2003.11a
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    • pp.15-18
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    • 2003
  • Ta-Ti metal alloy is proposed for alternate gate electrode of ULSI MOS device. Ta-Ti alloy was deposited directly on $SiO_2$ by a co-sputtering method and good interface property was obtained. The sputtering power of each metal target was 100W. Thermal and chemical stability of the electrode was studied by annealing at $500^{\circ}C$ and $600^{\circ}C$ in Ar ambient. X-ray diffraction was measured to study interface reaction and EDX(energy dispersive X-ray) measurement was performed to investigate composition of Ta and Ti element. Electrical properties were evaluated on MOS capacitor, which indicated that the work function of Ta-Ti metal alloy was ${\sim}4.1eV$ compatible with NMOS devices. The measured sheet resistance of alloy was lower than that of poly silicon.

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NOx Gas Detection Characterization with Vgs in the MWCNT Gas Sensor of MOS-FET Type (MOS-FET구조의 MWCNT 가스센서에서 Vgs의 변화에 따른 NOx 가스 검출 특성)

  • Kim, Hyun-Soo;Park, Yong-Seo;Jang, Kyung-Uk
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.27 no.4
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    • pp.257-261
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    • 2014
  • Carbon nanotubes (CNT) has the excellent physical characteristics in the sensor, medicine, manufacturing and energy fields, and it has been studied in those fields for the several years. We fabricated the NOx gas sensors of MOS-FET type using the MWCNT. The fabricated sensor was used to detect the NOx gas for the variation of $V_{gs}$ (gate-source voltage) with the ambient temperature. The gas sensor absorbed the NOx gas molecules showed the decrease of resistance, and the sensitivity of sensor was reduced by the NOx gas molecules accumulated on the MWCNT surface. Furthermore, when the voltage ($V_{gs}$) was applied to the gas sensor, the term of the decrease in resistance was increased. On the other hand, the sensor sensitivity for the injection of NOx gas was the highest value at the ambient temperature of $40^{\circ}C$. We also obtained the adsorption energy ($40^{\circ}C$) using the Arrhenius plots by the reduction of resistance due to the $V_{gs}$ voltage variations. As a result, we obtained that the adsorption energy also was increased with the increasement of the applied $V_{gs}$ voltages.

Thermal Resistance Characteristics and Fin-Layout Structure Optimization by Gate Contact Area of FinFET and GAAFET (FinFET 및 GAAFET의 게이트 접촉면적에 의한 열저항 특성과 Fin-Layout 구조 최적화)

  • Cho, Jaewoong;Kim, Taeyong;Choi, Jiwon;Cui, Ziyang;Xin, Dongxu;Yi, Junsin
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.34 no.5
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    • pp.296-300
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    • 2021
  • The performance of devices has been improved with fine processes from planar to three-dimensional transistors (e.g., FinFET, NWFET, and MBCFET). There are some problems such as a short channel effect or a self-heating effect occur due to the reduction of the gate-channel length by miniaturization. To solve these problems, we compare and analyze the electrical and thermal characteristics of FinFET and GAAFET devices that are currently used and expected to be further developed in the future. In addition, the optimal structure according to the Fin shape was investigated. GAAFET is a suitable device for use in a smaller scale process than the currently used, because it shows superior electrical and thermal resistance characteristics compared to FinFET. Since there are pros and cons in process difficulty and device characteristics depending on the channel formation structure of GAAFET, we expect a mass-production of fine processes over 5 nm through structural optimization is feasible.