• 한국전기전자재료학회논문지
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• 제22권12호
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• pp.1063-1066
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• 2009

In this study, we fabricated pentacene organic thin film trasistors(OTFTs) which used aluminum oxide as the gate insulator. Aluminum oxide for OTFTs was deposited on glass substrate with a different deposition rate by E-beam evaporation. In case of the deposition rate of $0.1\;{\AA}$, the fabricated aluminum oxide gate insulating OTFT showed a threshold voltage of -1.36 V, an on/off current ratio of $1.9{\times}10^3$ and field effect mobility $0.023\;cm^2/V_s$.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2018년도 춘계학술대회
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• pp.171-172
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• 2018

Dual gate L-shaped tunnel field-effect-transistor (DG-LTFET) is presented in this study. DG-LTFET achieves near vertical subthreshold slope (SS) and its ON current is also found to be higher then both conventional TFET and LTFET. This device could serve as a potential replacement for conventional complimentary metal-oxide-semiconductor (CMOS) technology.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2002년도 추계종합학술대회
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• pp.494-497
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• 2002

본 논문에서는 halo doping profile을 갖는 나노구조 LDD MOSFET의 문턱전압에 대한 시뮬레이션 결과를 나타내었다. 소자 크기는 generalized scaling을 사용하여 100nm에서 40nm까지 스케일링하였다. Van Dort Quantum Correction Model(QM)을 사용하여 정전계 스케일링과 정전압 스케일링에 대한 문턱 전압과 각각의 게이트 oxide 두께에 대한 direct tunneling 전류를 조사하였다. 게이트 길이가 감소할 때 정전계 스케일링에서는 문턱전압이 감소하고, 정전압 스케일링에서는 문턱전압이 증가하는 것을 알 수 있었고, 게이트 oxide두께가 감소할 때 direct tunneling 전류는 증가함을 알 수 있었다. 감소하는 채널 길이를 갖는 MOSFET 문턱전압에 대한 roll-off 특성을 최소화하기 위해 generalized scaling에서 $\alpha$값은 1에 가깝게 되는 것을 볼 수 있었다.

• 한국전기전자재료학회논문지
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• 제37권5호
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• pp.507-511
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• 2024

Various process modifications have been used to minimize SiO₂ gate oxide aging in metal-oxide-semiconductor field-effect transistors (MOSFETs). In particular, post-metallization annealing (PMA) with a deuterium ambient can effectively eliminate both bulk traps and interface traps in the gate oxide. However, even with the use of PMA, it remains difficult to prevent high levels of radiation-induced gate oxide damage such as total ionizing dose (TID) during long-term missions. In this context, additional low-temperature heat treatment (LTHT) is proposed to recover from radiation-induced damage. Positive traps in the damaged gate oxide can be neutralized using LTHT, thereby prolonging device reliability in harsh radioactive environments.

• 한국전기전자재료학회논문지
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• 제28권11호
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• pp.698-703
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• 2015

In this study, we fabricated the dual gate (DG) ion-sensitive field-effect-transistor (ISFET) with flexible polyimide (PI) extended gate (EG). The DG ISFETs significantly enhanced the sensitivity of pH in electrolytes from 60 mV/pH to 1152.17 mV/pH and effectively improved the drift and hysteresis phenomenon. This is attributed to the capacitive coupling effect between top gate and bottom gate insulators of the channel in silicon-on-transistor (SOI) metal-oxide-semiconductor (MOS) FETs. Accordingly, it is expected that the PI-EG based DG-ISFETs is promising technology for high-performance flexible biosensor applications.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제43회 하계 정기 학술대회 초록집
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• pp.350-350
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• 2012

본 연구에서는 Oxide 두께가 각각 4, 6 nm인 Symmetric NMOSFET의 전기적 특성 분석에 관한 연구를 진행하였다. 게이트 전압에 따른 Drain saturation current (IDSAT), Threshold Voltage(VT) 및 드레인 전압에 따른 Off-states 특성 변화를 분석하였다. 소자 측정 결과 oxide 두께가 4 nm인 경우 Vt는 0.3 V, IDSAT은 73 ${\mu}A$ (@VD=0.05)로, oxide 두께가 6 nm인 경우 Vt는 0.65 V, IDSAT은 66 ${\mu}A$ (@VD=0.05)로 각각 측정되었다. 이는 oxide 두께가 얇은 경우 게이트 전압 인가 시 Electric field 증가에 따른 것으로 판단된다. 또한 드레인 전압 인가에 따른 소자 특성 분석 결과 oxide 두께가 4nm인 경우 급격한 Gate leakage 증가를 보였으며, 이에 따라 Off-state에서의 leakage current가 증가함을 확인하였다. 본 연구는 Oxide 두께에 따른 MOSFET 소자의 전기적 특성 분석을 위해 진행되었으며, 상기 결과와 같이 oxide 두께 가변은 Idsat, Vt, leakage current 등의 주요 파라미터에 영향을 주어 NMOSFET 소자의 전기적 특성을 변화시킴을 확인하였다.

• 전기전자학회논문지
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• 제28권1호
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• pp.46-52
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• 2024

이번 연구에서 우리는 게이트 산화막을 형성하기 위해 Si을 증착한 후 산화시킨 SiC MOSFET의 전기적 특성을 연구했다. 고품질의 Si/SiO₂ 계면을 제작하기 위해 얇은 Si 층을 SiC epi 층 위에 약 20 nm을 증착한 후 산화하여 게이트 산화막을 약 55 nm로 형성했다. SiC를 산화하여 게이트 산화막을 제작한 소자와 계면 트랩 밀도, 온저항, 전계-효과 이동도의 측면에서 비교했다. 위 소자는 향상된 계면 트랩 밀도 (~8.18 × 10¹¹ eV^-1cm^-2), 전계-효과 이동도 (27.7 cm²/V·s), 온저항 (12.9 mΩ·cm²)을 달성하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제10권3호
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• pp.203-212
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• 2010

In this paper, we present an analytical model for the first eigen energy level ($E_0$) of the carriers in the inversion layer in present generation MOSFETs, having ultrathin gate oxides and high substrate doping concentrations. Commonly used approaches to evaluate $E_0$ make either or both of the following two assumptions: one is that the barrier height at the oxide-semiconductor interface is infinite (with the consequence that the wave function at this interface is forced to zero), while the other is the triangular potential well approximation within the semiconductor (resulting in a constant electric field throughout the semiconductor, equal to the surface electric field). Obviously, both these assumptions are wrong, however, in order to correctly account for these two effects, one needs to solve Schrodinger and Poisson equations simultaneously, with the approach turning numerical and computationally intensive. In this work, we have derived a closed-form analytical expression for $E_0$, with due considerations for both the assumptions mentioned above. In order to account for the finite barrier height at the oxide-semiconductor interface, we have used the asymptotic approximations of the Airy function integrals to find the wave functions at the oxide and the semiconductor. Then, by applying the boundary condition at the oxide-semiconductor interface, we developed the model for $E_0$. With regard to the second assumption, we proposed the inclusion of a fitting parameter in the wellknown effective electric field model. The results matched very well with those obtained from Li's model. Another unique contribution of this work is to explicitly account for the finite oxide-semiconductor barrier height, which none of the reported works considered.

• 한국전기전자재료학회논문지
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• 제17권7호
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• pp.713-717
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• 2004

In this study, the etched trench properties including cross-sectional profile, surface roughness, and crystalline defects were investigated depending on the various silicon etching and additive gases, For the case of HBr$He-O_2SiF_4$ trench etching gas mixtures, the excellent trench profile and minimum defects in the silicon trench were achieved. Due to the residual oxide film grown by the additive oxygen gas, which acts as a protective layer during trench etching, the undercut and defects generation in the trench were suppressed. To improve the electrical characteristics of trench gate, the hydrogen annealing process after trench etching was also adopted. Through the hydrogen annealing, the trench corners might be rounded by the silicon atomic migration at the trench corners having high potential. The rounded trench corner can afford to reduce the gate electric field and grow a uniform gate oxide. As a result, dielectric strength and TDDB characteristics of the hydrogen annealed trench gate oxide were remarkably increased compared to the non-hydrogen annealed one.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권5호
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• pp.530-537
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• 2013

An explicit surface potential calculation method of gate-all-around MOSFET (GAAMOSFET) devices which takes into account both interface trap charge and varying doping levels is presented. The results of the method are extensively verified by numerical simulation. Results from the model are used to find qualitative and quantitative effect of interface trap charge on subthreshold slope (SS) of GAAMOSFET devices. Further, design constraints of GAAMOSFET devices with emphasis on the effect of interface trap charge on device SS performance are investigated.