• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 하계학술대회 논문집
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• pp.45-49
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• 2001

We have investigated physical and electrical properties of the Hf $O_2$/HfS $i_{x}$/ $O_{y}$ thin film for alternative gate dielectrics in the metal-oxide-semiconductor device. The oxidation of Hf deposited directly on the Si substrate results in the H $f_{x}$/ $O_{y}$ interfacial layer and the high-k Hf $O_2$film simultaneously. Interestingly, the post-oxidation N2 annealing of the H102/H1Si70y thin films reduces(increases) the thickness of an amorphous HfS $i_{x}$/ $O_{y}$ layer(Hf $O_2$ layer). This phenomenon causes the increase of the effective dielectric constant, while maintaining the excellent interfacial properties. The hysteresis window in C-V curves and the midgap interface state density( $D_{itm}$) of Hf $O_2$/HfS $i_{x}$/ $O_{y}$ thin films less than 10 mV and ~3$\times$10$^{11}$ c $m^{-2}$ -eV without post-metallization annealing, respectively. The leakage current was also low (1$\times$10-s A/c $m^2$ at $V_{g}$ = +2 V). It is believed that these excellent results were obtained due to existence of the amorphous HfS $i_{x}$/ $O_{y}$ buffer layer. We also investigated the charge trapping characteristics using Fowler-Nordheim electron injection: We found that the degradation of Hf $O_2$/HfS $i_{x}$/ $O_{y}$ gate oxides is more severe when electrons were injected from the gate electrode.e electrode.e.e electrode.e.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 추계학술대회 논문집 Vol.15
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• pp.163-166
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• 2002

We investigated structural and electrical properties of Metal-Oxide-Semiconductor(MOS) structure using Hafnium $oxide(HfO_{2})$ as high-k gate dielectric material. $HfO_{2}$ films are ultrathin gate dielectric material witch have a thickness less than 2.0nm， so it is spotlighted to be substituted $SiO_{2}$ as gate dielectric material. In this paper We have grown $HfO_{2}$ films with pt electrode on P-type Silicon substrate by RF magnetron sputtering system using $HfO_{2}$ target and oserved the property of semiconductor-oxide interface. Using pt electrode, it is necessary to be annealed at ${300^{\circ}C}$. This process is to increase an adhesion ratio between $HfO_{2}$ films with pt electrode. In film deposition process, the deposition time of $HfO_{2}$ films is an important parameter. Structura1 properties are invetigated by AES depth profile, and electrical properties by Capacitance-Voltage characteristic. Interface trap density are measured to observe the interface between $HfO_{2}$ with Si using High-frequency(1MHz) C-V and Quasi - static C-V characteristic.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권2호
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• pp.1292-1294
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• 2007

In this report, the effects of chemical surface treatments of ITO gate electrodes of OTFTs have been studied by using acid and base solutions. As a result, it is observed that the threshold voltage of OTFTs could be influenced and modified by the surface treatments. The device with an ITO gate electrode surface-treated by a base solution shows the lowest threshold voltage of -7.66 V, while the threshold voltages are about -13.51 V and -15.3 V for the devices without a surface treatment and with the acid solution treatment, respectively. It is thought that the work function of ITO electrode surface might be affected by the surface treatments, thereby influencing the threshold voltage.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2004년도 Asia Display / IMID 04
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• pp.851-854
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• 2004

By approaching the counter electrode to the CNT emitter, remarkable reduction of the cathode operating voltage has been accomplished in the under-gate CNT cathode structure. The peak emission current density of 2.5 ms/$cm^2$, which is sufficient for high brightness CNT field emission display, was obtained at the cathode-to-gate voltage of 57 V when the CNT-to-counter electrode gap was 2.2 ${\mu}m$. The gate current was less than 10 % of the anode current. The CNT cathode with low driving voltage can help the cost-effective field emission display implemented.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2008년도 International Meeting on Information Display
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• pp.254-257
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• 2008

We have investigated the effect of source/drain electrode deposition method on a performance of top gate structured ZnO TFT performance. TFT using S/D of ITO film, consisted of bi-layer which deposited by ion beam assisted sputtering at the initial stage then deposited by DC magnetron sputtering, showed better performance compared to that using S/D of ITO deposited by just DC magnetron sputtering. Two ITO films exhibited different grain shapes and these resulted in different etching properties. We also suspect that charge trapping on the glass substrate (back channel) during the ITO film deposition may influence the characteristics of top gate structured ZnO TFT.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.883-886
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• 1999

We deposited tungsten gate electrode on gate SiO$_2$by thermal LPCVD with WF$_{6}$, SiH$_4$ and H$_2$. The resistivity was ~10$\mu$Ωcm and exhibited good adhesion ability on oxide when the temperature was higher than 40$0^{\circ}C$. We find that, however, both the low-field current and the charge-trapping characteristics were inferior to the control devices. The oxide degradation by fluorine during the tungsten deposition must be minimized to use the tungsten as alternative gate electrode.e.

• 한국전기전자재료학회논문지
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• 제13권7호
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• pp.557-562
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• 2000

160nm thick amorphous Si and polycrystalline Si were each deposited on to 10nm thick SiO$_2$, Co monolayer and Co/Ti bilayer were sequentially evaporated to form Co-polycide. Then MOS capacitors were fabricated by BF$_2$ ion-implantation. The characteristics of the fabricated capacitor samples depending upon the drive-in annel conductions were measured to study the effects of thermal stability of CoSi$_2$and dopant redistribution on electrical properties of Co-polycide gates. Results for capacitors using Co/Ti bilayer and drive-in annealed at 80$0^{\circ}C$ for 20~40sec. showed excellent C-V characteristics of gate electrode.

• Transactions on Electrical and Electronic Materials
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• 제2권1호
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• pp.32-38
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• 2001

A new small sized Lateral Trench electrode Insulated Gate Bipolar Transistor(LTEIGBT) was proposed to improve the characteristics of conventional Lateral IGBT (LIGBT) and Lateral Trench gate IGBT (LTIGBT). The entire electrode of LTEIGBT was replace with trench-type electrode. The LTEIGBT was designed so that the width of device was no more than 19 ㎛. The Latch-up current densities of LIGBT, LTIGBT and the proposed LTEIGBT were 120A/㎠, 540A/㎠, and 1230A/㎠, respectively. The enhanced latch-up capability of the LTEIGBT was obtained through holes in the current directly reaching the cathode via the p+ cathode layer underneath n+ cathode layer. The forward blocking voltage of the LTEIGBT is 130V. Conventional LIGBT and LTIGBT of the same size were no more than 60V and 100V, respectively. Because the the proposed device was constructed of trench-type electrodes, the electric field moved toward trench-oxide layer, and punch through breakdown of LTEIGBT is occurred, lately.

• 한국세라믹학회지
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• 제30권1호
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• pp.55-61
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• 1993

In the WSi2/CVD-Si/SiO2 polycide structure, electrode resistance and its property were studied as a function of deposition temperature and thickness of CVD-Si, diffusion condition of POCl3, and WSi2 being deposited or not. Resistivity of poly-Si is decreased with increment of thickness in the case of POCl3 diffusion of low sheet resistance, but it is increased in the case of high sheet resistance. The resistivity of amorphous-Si is generally lower than that of poly-Si. Initial sheet resistance of poly-Si/WSi2 gate electrode is affected by the thickness and resistance of poly-Si layer, but final resistance after anneal, 900$^{\circ}C$/30min/N2, is only determined by WSi2 layer. Flourine diffuses into SiO2, but tungsten does not. In spite of out-diffusion of phosphorus into WSi2 layer, the sheet resistance is not changed.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2005년도 추계학술대회 논문집
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• pp.506-508
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• 2005

In general, organic TFTs are comprised of four components: gate electrode, gate dielectric, organic active semiconductor layer, and source and drain contacts. The TFT current, in turn, is typically determined by channel length and width, carrier field effect mobility, gate dielectric thickness and permittivity, contact resistance, and biasing conditions. More recently, a number of techniques and processes have been introduced to the fabrication of OTFT circuits and displays that aim specifically at reduced fabrication cost. These include microcontact printing for the patterning of metals and dielectrics, the use of photochemically patterned insulating and conducting films, and inkjet printing for the selective deposition of contacts and interconnect pattern. In the fabrication of organic TFTs, microcontact printing has been used to pattern gate electrodes, gate dielectrics, and source and drain contacts with sufficient yield to allow the fabrication of transistors. We were fabricated a pentacene OTFTs on flexible PEN film. Au/Cr was used for the gate electrode, parylene-c was deposited as the gate dielectric, and Au/Cr was chosen for the source and drain contacts; were all deposited by ion-beam sputtering and patterned by microcontact printing and lift-off process. Prior to the deposition of the organic active layer, the gate dielectric surface was treated with octadecyltrichlorosilane(OTS) from the vapor phase. To complete the device, pentacene was deposited by thermal evaporation and patterned using a parylene-c layer. The device was shown that the carrier field effect mobility, the threshold voltage, the subthreshold slope, and the on/off current ratio were improved.