• Advances in nano research
• /
• 제3권1호
• /
• pp.49-54
• /
• 2015

The structure represents symmetrical metal electrode (gate 1) - front $SiO_2$ layer - n-Si nanowire FET - buried $SiO_2$ layer - metal electrode (gate 2). At the symmetrical gate voltages high conductive regions near the gate 1 - front $SiO_2$ and gate 2 - buried $SiO_2$ interfaces correspondingly, and low conductive region in the central region of the NW are formed. Possibilities of applications of nanosize FETs at the deep inversion and depletion as a distributed capacitance are demonstrated. Capacity density is an order to ${\sim}{\mu}F/cm^2$. The charge density, it distribution and capacity value in the nanowire can be controlled by a small changes in the gate voltages. at the non-symmetrical gate voltages high conductive regions will move to corresponding interfaces and low conductive region will modulate non-symmetrically. In this case source-drain current of the FET will redistributed and change current way. This gives opportunity to investigate surface and bulk transport processes in the nanosize inversion channel.

• 대한전기학회논문지:전기물성ㆍ응용부문C
• /
• 제50권10호
• /
• pp.532-535
• /
• 2001

The sputtering condition of Cr thin film was established in order to get Cr gate electrode having a vertical wall structure for Mo-tip FEA. In case of Mo-tip FEA which had a vertically-etched Cr gate electrode, the field enhancement factor, was relatively increased and so the field emission performance in terms of turn-on voltage, emission current and trans-conductance could be improved when compared with the devices having a tapered gate wall.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2003년도 학술대회 논문집 전문대학교육위원
• /
• pp.24-27
• /
• 2003

In this paper, We make experiment on two methode for GaAs MESFET with temperature variation. One method, we mesure gate leakage current at open source electrode. another we mesure gate leakage current at short source electrode. The difference of two current has been tested and provide that the existence of another source to Schottky barrier height against the image force lowering effect.

• 한국전기전자재료학회논문지
• /
• 제17권3호
• /
• pp.259-266
• /
• 2004

In this paper. a new two types of EST(Emitter Switched Thyristor) structures are proposed to improve the electrical characteristics including the current saturation capability. Besides, the two dimensional numerical simulations were carried out using MEDICI to verify the validity of the device and examine the electrical characteristics. First, a vortical trench electrode EST device is proposed to improve snap-back effect and its blocking voltage. Second, a dual trench gate EST device is proposed to obtain high voltage current saturation characteristics and high blocking voltage and to eliminate snap-back effect. The two proposed devices have superior electrical characteristics when compared to conventional devices. In the vertical trench electrode EST, the snap-back effect is considerably improved by using the vertical trench gate and cathode electrode and the blocking voltage is one times better than that of the conventional EST. And in the dual trench gate EST, the snap-back effect is completely removed by using the series turn-on and turn-off MOSFET and the blocking voltage is one times better than that of the conventional EST. Especially current saturation capability is three times better than that of the other EST.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2002년도 하계학술대회 논문집
• /
• pp.354-357
• /
• 2002

Thermally grown gate oxide on 4H-SiC wafer was investigated. The oxide layers were grown at l150$^{\circ}C$ varying the carrier gas and post activation annealing conditions. Capacitance-Voltage(C-V) characteristic curves were obtained and compared using various gate electrode such as Al, Ni and poly-Si. The interface trap density can be reduced by using post oxidation annealing process in Ar atmosphere. All of the samples which were not performed a post oxidation annealing process show negative oxide effective charge. The negative oxide effective charges may come from oxygen radical. After the post oxidation annealing, the oxygen radicals fixed and the effective oxide charge become positive. The effective oxide charge is negative even in the annealed sample when we use poly silicon gate. Poly silicon layer was dope by POCl$_3$ process. The oxide layer may be affected by P ions in poly silicon layer due to the high temperature of the POCl$_3$ doping process.

• 한국전기전자재료학회논문지
• /
• 제18권2호
• /
• pp.120-124
• /
• 2005

In this work, MOS capacitors were used to study the electrical properties of Mo gate electrode deposited on ZrO$_2$. The workfunctions of Mo gate extracted from C-V curves were appropriate for PMOS. Thermal stability of Mo metal was investigated by analyzing the variations of workfunction and EOT(effective oxide thickness) after 600, 700, and 800 $^{\circ}C$ RTA(rapid thermal annealing). It was found that Mo gate was stable up to 800 $^{\circ}C$ with underlying ZrO$_2$. The resistivities of Mo were 35$\mu$Ω$.$cm∼ 75$\mu$Ω$.$cm. These values are lower than those of heavily doped polysilicon. Based on these measurements, it can be concluded that Mo metal gate with ZrO$_2$ gate insulator is an excellent gate material for PMOS.

• 한국정밀공학회지
• /
• 제31권6호
• /
• pp.497-504
• /
• 2014

The digital signage display is actively researched as the next generation of large FPD. To commercialize those digital signage display, the manufacturing cost must be downed with printing method instead of conventional photolithography. Here, we demonstrate a reverse offset printed TFT electrodes for the digital signage display. For the fabricated source/drain and gate electrode, we used Ag ink, silicone blanket, Clich$\acute{e}$ and reverse offset printer. We printed uniform TFT electrode patterns with narrow line width(10 ${\mu}m$ range) and thin thickness(nm range). In the end the printing source/drain and gate electrode are successfully achieved by optimization of experimental conditions such as Clich$\acute{e}$ surface treatment, ink coating process, delay time, off/set process and curing temperature. Also, we checked that the printing align accuracy was within 5 ${\mu}m$.

• 전자공학회논문지D
• /
• 제34D권6호
• /
• pp.43-49
• /
• 1997

Tungsten poycide has studied gate oxide reliability and dielectric strength charactristics as the composition of gate electrode which applied submicron on CMOS and MOS device for optimizing gate electrode resistivity. The gate oxide reliability has been tested using the TDDB(time dependent dielectric breakdwon) and SCTDDB (stepped current TDDB) and corelation between polysilicon and WSi$_{2}$ layer. iN the case of high intrinsic reliability and good breakdown chracteristics on polysilicon, confirmed that tungsten polycide layer is a better reliabilify properities than polysilicon layer. Also, hole trap is detected on the polysilicon structure meanwhile electron trap is detected on polycide structure. In the case of electron trap, the WSi$_{2}$ layer is larger interface trap genration than polysilicon on large POCL$_{3}$ doping time and high POCL$_{3}$ doping temperature condition. WSi$_{2}$ layer's leakage current is less than 1 order and dielectric strength is a larger than 2MV/cm.

• 한국정보통신학회논문지
• /
• 제13권7호
• /
• pp.1393-1398
• /
• 2009

본 연구는 LCD용 비정질 실리콘박막트랜지스터의 제조공정중 가장 중요한 식각 공정에서 각 박막의 특성에 맞는 습식 및 건식식각공정을 개발하여 소자의 특성을 안정시키고자 한다. 본 연구의 수소화 된 비정질 실리콘 박막 트랜지스터는 Inverted Staggered 형태로 게이트 전극이 하부에 있다. 실험 방법은 게이트전극, 절연층, 전도층, 에치스토퍼 및 포토레지스터층을 연속 증착한다. 스토퍼층을 게이트 전극의 패턴으로 남기고, 그 위에 n+a-Si:H 층 및 NPR(Negative Photo Resister)을 형성시킨다. 상부 게이트 전극과 반대의 패턴으로 NPR층을 패터닝하여 그것을 마스크로 상부 n+a-Si:H 층을 식각하고, 남아있는 NPR층을 제거 한다. 그 위 에 Cr층을 증착한 후 패터닝 하여 소오스-드레인 전극을 위한 Cr층을 형성시켜 박막 트랜지스터를 제조한다. 여기서 각 박막의 패터닝은 식각 공정으로 각단위 박막의 특성에 맞는 건식 및 습식식각 공정이 필요하다. 제조한 박막 트랜지스터에서 가장 흔히 발생되는 문제는 주로 식각 공정시 over 및 under etching 이며, 정확한 식각을 위하여 각 박막에 맞는 식각공정을 개발하여 소자의 최적 특성을 제공하고자한다. 이와 같이 공정에 보다 엄격한 기준의 건식 및 습식식각 공정 그리고 세척 등의 처리공정을 정밀하게 실시하여 소자의 특성을 확실히 개선 할 수 있었다.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2009년도 하계학술대회 논문집
• /
• pp.104-104
• /
• 2009

Critical dimensions has rapidly shrunk to increase the degree of integration and to reduce the power consumption. However, it is accompanied with several problems like direct tunneling through the gate insulator layer and the low conductivity characteristic of poly-silicon. To cover these faults, the study of new materials is urgently needed. Recently, high dielectric materials like $Al_2O_3$, $ZrO_2$ and $HfO_2$ are being studied for equivalent oxide thickness (EOT). However, poly-silicon gate is not compatible with high-k materials for gate-insulator. To integrate high-k gate dielectric materials in nano-scale devices, metal gate electrodes are expected to be used in the future. Currently, metal gate electrode materials like TiN, TaN, and WN are being widely studied for next-generation nano-scale devices. The TaN gate electrode for metal/high-k gate stack is compatible with high-k materials. According to this trend, the study about dry etching technology of the TaN film is needed. In this study, we investigated the etch mechanism of the TaN thin film in an inductively coupled plasma (ICP) system with $O_2/BCl_3/Ar$ gas chemistry. The etch rates and selectivities of TaN thin films were investigated in terms of the gas mixing ratio, the RF power, the DC-bias voltage, and the process pressure. The characteristics of the plasma were estimated using optical emission spectroscopy (OES). The surface reactions after etching were investigated using X-ray photoelectron spectroscopy (XPS) and auger electron spectroscopy (AES).