• Journal of Electrical Engineering and Technology
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• v.13 no.4
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• pp.1528-1538
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• 2018

In this paper, configuration of $1-{\phi}$ seven-level boost DC-link cascade based reversing voltage multilevel inverter (BDCLCRV MLI) is proposed for uninterrupted power supply (UPS) applications. It consists of three level boost converter, level generation unit and full bridge circuit for polarity generation. When compared with conventional boost cascaded H-bridge MLI configurations, the proposed system results in reduction of DC sources, reduced power switches and gate drive requirements. Inverter switching is accomplished by providing appropriate switching angles that is generated by any optimization switching angle techniques. Here, round modulation control (RMC) method is taken as the optimization method and switching angles are derived and the same is compared with various switching angles methods i.e., equal-phase (EP) method, and half-equal-phase (HEP) method which results in improved quality of obtained AC power with lowest total harmonic distortion (THD). Reduction in DC sources and switch count makes the system more cost effective. A simulation and prototype model of $1-{\phi}$ seven-level BDCLCRV MLI system is developed and its performance is analyzed for various operating conditions.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.10a
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• pp.145-148
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• 2016

In this paper, we propose a design of Intra Prediction angular mode decision for high-performance HEVC encoder. Intra Prediction works by performing all 35 modes for efficient encoding. However, in order to process all of the 35 modes, the computational complexity and operational time required are high. Therefore, this paper proposes comparing the difference in the value of the original image pixel, using an algorithm that determines Angular mode efficiently. This new algorithm reduces the Hardware size. The hardware which is proposed was designed using Verilog HDL and was implemented in 65nm technology. Its gate count is 14.9k and operating speed is 2GHz.

• Journal of IKEEE
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• v.24 no.4
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• pp.1172-1175
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• 2020

Automotive ECU integrates CPU core, IVN controller, memory interface, sensor interface, I/O interface, and so on. Current automotive ECUs are often developed with proprietary processor architectures. However, demends for standard processors such as ARM and RISC-V increase rapidly for saftware compatibility in autonomous vehicles and connected cars. In this paper, an automotive ECU is designed for parking assist system based on RISC-V with open instruction set architecture. It includes 32b RISC-V CPU core, IVN controllers such as CAN and LIN, memory interfaces such as ROM and SRAM, and I/O interfaces such as SPI, UART, and I2C. Fabricated in 65nm CMOS technology, its operating frequency, area, and gate count are 50MHz, 0.37㎟, and 55,310 gates, respectively.

• Nuclear Engineering and Technology
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• v.56 no.1
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• pp.56-63
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• 2024

In high radiation fields, gamma cameras suffer from pulse pile-up, resulting in poor energy resolution, count losses, and image distortion. To overcome this problem, various methods have been introduced to reduce the size of the aperture or pixel, reject the pile-up events, and correct the pile-up events, but these technologies have limitations in terms of mechanical design and real-time processing. The purpose of this study is to develop a real-time gamma camera to evaluate the radioactive contamination in high radiation fields. The gamma camera is composed of a pinhole collimator, NaI(Tl) scintillator, position sensitive photomultiplier (PSPMT), signal processing board, and data acquisition (DAQ). The pulse pile-up is corrected in real-time with a field programmable gate array (FPGA) using the start time correction (STC) method. The STC method corrects the amplitude of the pile-up event by correcting the time at the start point of the pile-up event. The performance of the gamma camera was evaluated using a high dose rate ¹³⁷Cs source. For pulse pile-up ratios (PPRs) of 0.45 and 0.30, the energy resolution improved by 61.5 and 20.3%, respectively. In addition, the image artifacts in the ¹³⁷Cs radioisotope image due to pile-up were reduced.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.5 s.335
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• pp.55-62
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• 2005

In this paper, we propose an efficient symbol detection algorithm for space-frequency OFDM (SF-OFDM) transmit diversity scheme and present the implementation results of the SF-OFDM WLAN baseband processor with the proposed algorithm. When the number of sub-carriers in SF-OFDM scheme is small, the interference between adjacent sub-carriers may be generated. The proposed algorithm eliminates this interference in a parallel manner and obtains a considerable performance improvement over the conventional detection algorithm. The bit error rate (BER) performance of the proposed detection algorithm is evaluated by the simulation. In the case of 2 transmit and 2 receive antennas, at $BER=10^{-4}$ the proposed algorithm obtains about 3 dB gain over the conventional detection algorithm. The packet error rate (PER), link throughput, and coverage performance of the SF-OFDM WLAN with the proposed detection algorithm are also estimated. For the target throughput at $80\%$ of the peak data rate, the SF-OFDM WLAN achieves the average SNR gain of about 5.95 dB and the average coverage gain of 3.98 meter. The SF-OFDM WLAN baseband processor with the proposed algorithm was designed in a hardware description language and synthesized to gate-level circuits using 0.18um 1.8V CMOS standard cell library. With the division-free architecture, the total logic gate count for the processor is 945K. The real-time operation is verified and evaluated using a FPGA test system.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.3
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• pp.699-707
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• 2016

This paper proposes a low-complexity central processing unit (CPU) that is suitable for deeply embedded systems, including Internet of things (IoT) applications. The core features a 16-bit instruction set architecture (ISA) that leads to high code density, as well as a multicycle architecture with a counter-based control unit and adder sharing that lead to a small hardware area. A co-processor, instruction cache, AMBA bus, internal SRAM, external memory, on-chip debugger (OCD), and peripheral I/Os are placed around the core to make a system-on-a-chip (SoC) platform. This platform is based on a modified Harvard architecture to facilitate memory access by reducing the number of access clock cycles. The SoC platform and CPU were simulated and verified at the C and the assembly levels, and FPGA prototyping with integrated logic analysis was carried out. The CPU was synthesized at the ASIC front-end gate netlist level using a $0.18{\mu}m$ digital CMOS technology with 1.8V supply, resulting in a gate count of merely 7700 at a 50MHz clock speed. The SoC platform was embedded in an FPGA on a miniature board and applied to deeply embedded IoT applications.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.48 no.3
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• pp.62-70
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• 2011

Nowadays image sensor is an essential component in many multimedia devices, and it is covered by a color filter array to filter out specific color components at each pixel. We need a certain algorithm to combine those color components reconstructed a full color image from incomplete color samples output from an image sensor, which is called a demosaicking process. Most existing demosaicking algorithms are developed for ideal image sensors, but they do not work well for the practical cases because of dissimilar characteristics of each sensor. In this paper, we propose a new demosaicking algorithm in which the color filter characteristics are fully utilized to generate a good image. To demonstrate significance of our algorithm, we used a commerically available sensor, CBN385B, which is a sort of Honeycomb-style CFA(Color Filter Array) CCD image sensor. As a performance metric of the algorithm, PSNR(Peak Signal to Noise Ratio) and RGB distribution of the output image are used. We first implemented our algorithm in C-language for simulation on various input images. As a result, we could obtain much enhanced images whose PSNR was improved by 4~8 dB compared to the commonly idealized approaches, and we also could remove the inclined red property which was an unique characteristics of the image sensor(CBN385B).Then we implemented it in hardware to overcome its problem of computational complexity which made it operate slow in software. The hardware was verified on Spartan-3E FPGA(Field Programable Gate Array) to give almost the same performance as software, but in much faster execution time. The total logic gate count is 45K, and it handles 25 image frmaes per second.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.7
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• pp.61-68
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• 2008

In this paper, we propose an efficient hardware architecture and algorithm to increase an encoding process rate and implement a hardware for CABAC (Context Adaptive Binary Arithmetic Coding) which is used with one of the entropy coding ways for the latest video compression technique, H.264/AVC (Advanced Video Coding). CABAC typically provides a better high compression performance maximum 15% compared with CAVLC. However, the complexity of operation of CABAC is significantly higher than the CAVLC. Because of complicated data dependency during the encoding process, the complexity of operation is higher. Therefore, various architectures were proposed to reduce an amount of operation. However, they have still latency on account of complicated data dependency. The proposed architecture has two techniques to implement efficient pipeline architecture. The one is quick calculation of 7, 8th bits used to calculate a probability is the first step in Binary arithmetic coding. The other is one step reduced pipeline arcbitecture when the type of the encoded symbols is MPS. By adopting these two techniques, the required processing time was reduced about 27-29% compared with previous architectures. It is designed in a hardware description language and total logic gate count is 19K using 0.18um standard cell library.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.26-36
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• 2006

In this paper, we propose a cost-effective color filter may (CFA) demosaicing method for digital still cameras in which a single CCD or CMOS image sensor is used. Since a CFA is adopted, we must interpolate missing color values in the red, green and blue channels at each pixel location. While most state-of-the-art algorithms invest a great deal of computational effort in the enhancement of the reconstructed image to overcome the color artifacts, we focus on eliminating the color artifacts with low computational complexity. Using spatial correlation of the adjacent pixels, the edge-directional information of the neighbor pixels is used for determining the edge direction of the current pixel. We apply our method to the state-of-the-art algorithms which use edge-directed methods to interpolate the missing color channels. The experiment results show that the proposed method enhances the demosaiced image qualify from $0.09{\sim}0.47dB$ in PSNR depending on the basis algorithm by removing most of the color artifacts. The proposed method was implemented and verified successfully using verilog HDL and FPGA. It was synthesized to gate-level circuits using 0.25um CMOS standard cell library. The total logic gate count is 12K, and five line memories are used.

• The Korean Journal of Nuclear Medicine Technology
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• v.20 no.1
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• pp.20-23
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• 2016

Purpose Because of heart movement, PET image of heart is very blur. So, PET scan gated with ECG is necessary to improve a spatial resolution of heart PET image. In this study, we will evaluate a image quality of both gated $^{13}N-ammonia$ PET scan and non-gated one. Materials and Methods Before start a heart PET, we attached a ECG electrode on patients (n = 5, $aged=54{\pm}17$). And we started a list mode PET scan that used by a mCT40 PET/CT (siemens, germany) during 10 minute, injected $^{13}N-ammonia$ ($378{\pm}50MBq$) to a patients at same time. By using this list mode data, we reconstructed both gated PET image and non-gated PET image. Then we analysed a profiles of those images, performed a blind test, and subtracted a gated image on non-gated image. Results FWHM of a gated image is improved about 23% and there is a differency count distribution at a subtracted image from non-gated image to a gated image. But in case of blind test, everybody select the gated image as a better quality among each images. Conclusion As a result, we can find that image quality will improve by using gated PET scan. In additional, we can calculate a EF valve, apply QGS, QPS of PET. Therefore, the gated PET scan help improving an accuracy, applying a more information for a diagnosis.