• 대한전자공학회논문지SD
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• 제46권10호
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• pp.16-24
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• 2009

Independent-Gate-Mode Double-Gate(IGM-DG) MOSFET는 기존의 DG-MOSFET의 3-terminal 소자구조가 갖고 있는 한계에서 벗어나 front-gate와 back-gate를 서로 다른 전압으로 구동하는 것이 가능하다. IGM-DG를 이용함으로써 4번째 단자의 자유도에 의해 회로설계가 간단해 질 뿐 아니라, 집적도를 향상시킬 수 있는 장점을 가진다. 본 논문에서는 IGM-DG MOSFET를 사용하여 RF 수신단을 설계하였고, HSPICE 시뮬레이션을 통해 회로성능을 검증하고 소자의 특성변화에 따른 최적의 회로설계 방향을 제시하였다.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2002년도 International Meeting on Information Display
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• pp.717-720
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• 2002

In this work, the electrical characteristics of organic thin film transistors with the surface-treated organic gate insulators have been studied. For the surface treatment, the simple rubbing technique was used. The field effect mobilities of the devices with PVP gate insulator was improved about four times as high as those of TFTs without the insulator surface treatment.

• 한국재료학회지
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• 제24권3호
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• pp.135-139
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• 2014

To obtain the transistor with ambipolar transfer characteristics, IGZO/SiOC thin film transistor was prepared on SiOC with various polarities as a gate insulator. The interface between a channel and insulator showed the Ohmic and Schottky contacts in the bias field of -5V ~ +5V. These contact characteristics depended on the polarities of SiOC gate insulators. The transfer characteristics of TFTs were observed the Ohmic contact on SiOC with polarity, but Schottky contact on SiOC with low polarity. The IGZO/SiOC thin film transistor with a Schottky contact in a short range bias electric field exhibited ambipolar transfer characteristics, but that with Ohmic contact in a short range electric field showed unipolar characteristics by the trapping phenomenon due to the trapped ionized defect formation.

• Transactions on Electrical and Electronic Materials
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• 제14권1호
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• pp.28-31
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• 2013

A volcano shaped gated Si-FEA (silicon field emitter array) was simply fabricated using sputtering as a gate electrode deposition and lift-off for the removal of the oxide mask, respectively. Due to the limited step coverage of well-controlled sputtering and the high aspect ratio in Si dry etch caused by high RF power, it was possible to obtain Si FEAs with a stable volcano shaped gate structure and to realize the restriction of gate leakage current in field emission characteristics. For 100 tip arrays and 625 tip arrays, gate leakage currents were restricted to less than 1% of the anode current in spite of the volcano-shaped gate structure. It was also possible to keep the emitters stable without any failure between the Si cathode and gate electrode in field emission for a long time.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권1호
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• pp.41-45
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• 2012

We observed that in chemical vapor deposition (CVD) tungsten silicide (WSix) poly gate scheme, the gate oxide thickness decreases as gate length is reduced, and it intensifies the roll-off properties of transistor. This is because the fluorine diffuses laterally from WSix to the gate sidewall oxide in addition to its vertical diffusion to the gate oxide during gate re-oxidation process. When the channel length is very small, the gate oxide thickness is further reduced due to a relative increase of the lateral diffusion than the vertical diffusion. In DRAM cells where the channel length is extremely small, we found the thinned gate oxide is a main cause of poor retention time.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권1호
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• pp.156-161
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• 2017

This work presents a novel structure for junction-less tunneling field effect transistor (JL-TFET) with a floating gate over the source region. Introduction of floating gate instead of fixed metal gate removes the limitation of fabrication process suitability. The proposed device is based on a heavily n-type-doped Si-channel junction-less field effect transistor (JLFET). A floating gate over source region and a control-gate with optimized metal work-function over channel region is used to make device work like a tunnel field effect transistor (TFET). The proposed device has exhibited excellent ID-VGS characteristics, ION/IOFF ratio, a point subthreshold slope (SS), and average SS for optimized device parameters. Electron charge stored in floating gate, isolation oxide layer and body doping concentration are optimized. The proposed JL-TFET can be a promising candidate for switching performances.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
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• pp.173-174
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• 2006

In this paper we proposed transient model for NPT(Non Punch-Through) IGBT(Insulated Gate Bipolar Transistor) with gate resistances. As gate resistance increases, turn-off time increases. But If gate resistance is small, overshoot voltage increase. To analyze the effect of gate resistance, the transient model is made and the experiments are conducted. We used gate resistances of values; 8[$\Omega$], 140[$\Omega$], 810[$\Omega$] for simulations and experiments. We compared theoretical and experimental results and obtained good agreements.

• 한국실내디자인학회논문집
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• 제26권4호
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• pp.84-92
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• 2017

Just as the front gate is located at the meeting point between the house and the street, the Subject and the Other face each other the same way. This study examines the relationship between House(subject) and Stree (other) at the boundary of the Front Gate-Face. Pursuing the aspects of the changing Front Gate-Face accordingly to the attitude of the Subject facing the Other, this study tries to analyze the possibilities and significance of the hospitality Front Gate-Face with the ethical point of view of Levinas. As architectural instance, results of examining the Front Gate-Face of traditional houses in Korea, China and Japan are as follows. Front Gate-Face of China is characterized by self-centered introversion to interact with the external world (the other). Front Gate-Face of Japan is characterized by a humble submission to the group. Front Gate-Face of Korea shows however more flexible relationship orientations in terms of hospitality, compared to Japan or China. When looking through hospitality factors, accordingly to the above mentioned Korean hospitality characteristics, the possibilities seem not be exclusively bordered inside the conceptual category perimeter suggested by Levinas' concept of hospitality. It is almost impossible for the nowadays ever-strong privacy culture to not allow room for the architectural structure of an absolute hospitality toward others. However, this impossibility not being absolute, still yields a space for a significant possibility to explore.

• 전기전자학회논문지
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• 제26권3호
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• pp.500-505
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• 2022

본 연구에서는 새로운 구조의 dual gate tri-layer split channel 박막트랜지스터를 제작하였다. 전류 구동 능력을 향상시키기 위해 액티브 층의 양쪽에 게이트를 형성하였고 전하이동도를 증가시키기 위하여 액티브 층에서 채널이 형성되는 구간인 첫번째 층과 세번째 층에 전도성이 높은 ITO 층을 배치하였다. 추가적으로 분할 채널을 이용하여 채널의 series 저항을 낮추면서 분할한 채널의 측면에서도 accumulation을 유도하여 전하이동도를 향상시켰다. 기존의 single gate a-ITGZO 박막트랜지스터가 15 cm²/Vs의 전하이동도를 가지는 반면 dual gate tri-layer split channel 박막트랜지스터는 134 cm²/Vs의 높은 전하이동도를 가졌다.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2002년도 추계학술발표강연 및 논문개요집
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• pp.107-107
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• 2002