• Journal of Electrical Engineering and Technology
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• 제12권4호
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• pp.1619-1626
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• 2017

Electronic components that are used in high-level radiation environment require a semiconductor device having a radiation-hardened characteristic. In this paper, we proposed a radiation-hardened I-gate n-MOSFET (n-type Metal Oxide Semiconductors Field Effect Transistors) using a layout modification technique only. The proposed I-gate n-MOSFET structure is modified as an I-shaped gate poly in order to mitigate a radiation-induced leakage current in the standard n-MOSFET structure. For verification of its radiation-hardened characteristic, the M&S (Modeling and Simulation) of the 3D (3-Dimension) structure is performed by TCAD (Technology Computer Aided Design) tool. In addition, we carried out an evaluation test using a $Co^{60}$ gamma-ray source of 10kGy(Si)/h. As a result, we have confirmed the radiation-hardened level up to a total ionizing dose of 20kGy(Si).

• 전자공학회논문지A
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• 제32A권2호
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• pp.324-331
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• 1995

The leakage current characteristics of the low temperature processed LDD structure poly-Si TFT is analyzed. The excimer laser technology was applied to the recrystallization process of poly-Si film and the maximum processing temperature was retained under 600.deg.C. From the fabricated LDD space 0.3.mu.m to 3$\mu$m, the best on/off current ration could be obtained with the 1.3$\mu$m LDD space. And the threshold voltage did not increase more than 4V over 0.8$\mu$m LDD space. The characteristics of leakage current was compared to non-LDD structure TFT to analyze the mechanism of leakage current. Consequently, it could be concluded that the leakage current is strongly affected by the trap states as well as high electric field between gate and drain.

• 전기전자학회논문지
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• 제11권4호
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• pp.152-157
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• 2007

본 연구에서는 AlGaN/GaN HEMT (High electron mobility transistor)를 제작하고 20 mTorr의 챔버 압력과 15 sccm의 ${N_2}O$ 유량, 40 W의 RF 전력의 조건으로 원거리에서 형성된 플라즈마로 소스와 드레인 영역을 10초${\sim}$120초 동안 처리하여 HEMT의 전기적 특성을 관찰하였다. 상온에서 ${N_2}O$ 플라즈마에 처리한 경우 HEMT의 특성이 변화하지 않았으나 $200^{\circ}C$의 온도에서 10초 동안 처리한 경우 게이트 길이가 1um, 소스와 드레인 사이의 거리가 4um인 HEMT의 게이트 누설전류가 246 nA로부터 1.2 pA로 크게 감소하였다. 또한 25 um 떨어진 200um 폭의 두 활성층 사이 누설전류가 3 uA로부터 7 nA로 감소하였으며 720 ${\Omega}/{\box}$의 활성층의 면저항을 608 ${\Omega}/{\box}$로 감소시켜 도전율의 증가를 나타내기도 하였다. ${N_2}O$ 플라즈마의 처리에 의한 전기적 특성 개선은 10초 이내의 짧은 시간 동안 이루어지며 더 이상의 처리는 누설전류 특성 개선에 도움이 되지 않았다. 또한 ${N_2}O$ 플라즈마 처리로 개선된 특성은 $SiO_2$의 증착과 식각 후에도 개선된 특성이 유지되었다. ${N_2}O$ 플라즈마의 처리는 트랜지스터의 트랜스컨덕턴스와 드레인 전류의 증가, 드레인 전류의 차단특성의 개선에도 기여하여 고품위의 AlGaN/GaN HEMT 제작에 효과적으로 이용될 수 있음이 확인되었다.

• 전기전자학회논문지
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• 제24권1호
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• pp.194-199
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• 2020

본 논문에서는 비대칭 무접합 이중게이트 MOSFET에 대한 문턱전압이동을 상단과 하단 게이트 산화막 두께에 따라 분석하였다. 비대칭 구조에서는 상단과 하단 게이트 산화막 두께를 달리 제작할 수 있으므로 문턱전압이동을 일정하게 유지하면서 상단 게이트에서 발생할 수 있는 누설전류를 감소시키기 위하여 상단과 하단 산화막 두께를 조정할 수 있다. 이를 위하여 해석학적 문턱전압 모델을 제시하였으며 이 모델은 2차원 시뮬레이션 값과 잘 일치하였다. 결과적으로 일정한 문턱전압이동을 유지하면서 하단 게이트 산화막 두께를 감소시키면 상단 게이트 산화막 두께를 증가시킬 수 있어 상단 게이트에서 발생할 수 있는 누설전류를 감소시킬 수 있을 것이다. 특히 하단 게이트 산화막 두께가 증가하여도 문턱전압이동에는 큰 영향을 미치지 않는다는 것을 관찰하였다.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제48권8호
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• pp.577-579
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• 1999

DLC film remaining on device surface could be removed by eliminating AI sacrificial layer as a final step of lift-off process in the fabrication of DLC-coated Si-tip FEA. The field emission properties(I-V curves, hysteresis, and current fluctuation etc.) of the processed device were analyzed and the process was employed to 1.76 inch-sized FEA panel fabrication in order to evaluate its FED applicability.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2010년도 하계학술대회 논문집
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• pp.346-346
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• 2010

A capacitorless one transistor dynamic random access memory (1T-DRAM) on silicon-germanium-on-insulator substrate was investigated. SGOI technology can make high effective mobility because of lattice mismatch between the Si channel and the SiGe buffer layer. To evaluate memory characteristics of 1T-DRAM, the floating body effect is generated by impact ionization (II) and gate induced drain leakage (GIDL) current. Compared with use of impact ionization current, the use of GIDL current leads to low power consumption and larger sense margin.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1996년도 춘계학술대회 논문집
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• pp.90-93
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• 1996

The conduction mechanisms of the off-current in low temperature ($\leq$600$^{\circ}C$) processed polycrystalline silicon thin film transistors (LTP poly-Si TFT's) has been systematically studied. Especially, the temperature and bias dependence of the off-current between unpassivated and passivated poly-Si TFT's was investigated and compared. The off-current of unpassivated poly-Si TFT's is due to a resistive current at low gate and drain voltage, thermal emission current at high gate, low drain voltage, and field enhanced thermal emission current in the depletion region near the drain at high gate and drain voltage. After hydrogenation, it was observed that the off-currents were remarkably reduced by plasma-hydrogenation. It was also observed that the off-currents of the passivated poly-Si TFT's are more critically dependent on temperature rather than electric field.

• 한국전기전자재료학회논문지
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• 제21권2호
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• pp.104-110
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• 2008

In this paper we proposed a new source-drain structure for N-type MOSFET which can suppress the output resistance reduction of a device in saturation region due to soft break down leakage at high drain voltage when the gate is biased around relatively low voltage. When a device is generally used as a switch at high gate bias the current level is very important for the operation. but in electronic circuit like an amplifier we should mainly consider the output resistance for the stable voltage gain and the operation at low gate bias. Hence with T-SUPREM simulator we designed devices that operate at low gate bias and high gate bias respectively without a extra photo mask layer and ion-implantation steps. As a result the soft break down leakage due to impact ionization is reduced remarkably and the output resistance increases about 3 times in the device that operates at the low gate bias. Also it is expected that electronic circuit designers can easily design a circuit using the offered N-type MOSFET device with the better output resistance.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1995년도 하계학술대회 논문집 C
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• pp.1085-1087
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• 1995

A large leakage current may be one of the critical issues for poly-silicon thin film transistors(poly-Si TFTs) for LCD applications. In order to reduce the leakage current of poly-Si TFTs, several offset gated structures have been reported. However, those devices, where the offset length in the source region is not same as that in the drain region, exhibit the asymmetric electrical performances such as the threshold voltage shift and the variation of the subthreshold slope. The different offset length is caused by the additional mask step for the conventional offset structures. Also the self-aligned implantation may not be applicable due to the mis-alignment problem. In this paper, we propose a new fabrication method for poly-Si TFTs with a self-aligned offset gated structure by employing a photo resistor reflow process. Compared with the conventional poly-Si TFTs, the device is consist of two gate electrodes, of which one is the entitled main gate where the gate bias is employed and the other is the entitled subgate which is separate from both sides of the main gate. The poly-Si channel layer below the offset oxide is protected from the injected ion impurities for the source/drain implantation and acts as an offset region of the proposed device. The key feature of our new device is the offset lesion due to the offset oxide. Our experimental results show that the offset region, due to the photo resistor reflow process, has been successfully obtained in order to fabricate the offset gated poly-Si TFTs. The advantages of the proposed device are that the offset length in the source region is the same as that in the drain region because of the self-aligned implantation and the proposed device does not require any additional mask process step.

• 한국산학기술학회논문지
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• 제13권4호
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• pp.1789-1796
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• 2012

본 논문에서는 RFID 태그 칩 구동을 위한 새로운 고효율 CMOS 브리지 정류기를 설계하고 해석하였다. 동작 주파수가 높아짐에 따라 증가하는 게이트 누설전류의 주 통로가 되는 게이트 커패시턴스를 회로적인 방법으로 감소시키기 위해 제안한 정류기의 입력단을 두 개의 NMOS로 종속접속형으로 연결하여 설계하였으며, 이러한 종속접속형 입력단을 이용한 게이트 커패시턴스 감소 기법을 이론적으로 제시하였다. 또한 제안한 정류기의 출력특성은 고주파 소신호 등가회로를 이용하여 해석적으로 유도하였다. 일반적인 경우의 $50K{\Omega}$ 부하저항에 대해, 제안한 정류기는 915MHz의 UHF(for ISO 18000-6)에서는 28.9%, 2.45GHz의 마이크로파 대역 (for ISO 18000-4)에서는 15.3%의 전력변환효율을 보여, 915MHz에서 26.3%와 26.8%, 2.45GHz에서 13.2%와 12.6%의 전력변환효율을 보인 비교된 기존의 두 정류기에 비해 보다 개선된 전력변환효율을 보였다. 따라서 제안한 정류기는 다양한 종류의 RFID 시스템의 태그 칩 구동을 위한 범용 정류기로 사용될 수 있을 것이다.