• 제목/요약/키워드: Gate Insulator

검색결과 380건 처리시간 0.026초

a-Si TFT 제작시 RF-power 가변에 따른 전기적 특성

  • 백경현;정성욱;장경수;유경열;안시현;조재현;박형식;이준신
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2011년도 제40회 동계학술대회 초록집
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    • pp.116-116
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    • 2011
  • 오늘날 표시장치는 경량, 고밀도, 고해상도 대면적화의 요구에 의해 TFT-LCD의 발전이 이루어졌다. TFT에는 반도체 재료로서, Poly-Si을 사용하는 Poly-Si TFT와 a-Si:H를 이용하는 a-Si;H TFT가 있는데 a-Si는 $350^{\circ}C$ 이하의 저온으로 제작이 가능하여 많이 사용되고 있다. 이러한 방향에 맞추어 bottom gate 구조의 a-Si TFT 실험을 진행하였다. P-type silicon substrate ($0.01{\sim}0.02{\Omega}-cm$)에 gate insulator 층인 SiNx (SiH4 : NH3 = 6:60)를 200nm 증착하였다. 그리고 그 위에 active layer 층인 a-Si (SiH4 : H2 : He =2.6 : 10 : 100)을 다른 RF power를 적용하여 100 nm 증착하였다. 그 위에 Source와 Drain 층은 Al 120 nm를 evaporator로 증착하였다. active layer, gate insulator 층은 ICP-CVD 장비를 이용하여 증착하였으며, 공정온도는 $300^{\circ}C$ 로 고정하였다. active layer층 증착시 RF power는 100W, 300W, 500W, 600W로 가변하였고, width/length는 100 um/8um로 고정하였다. 증착한 a-Si layer층을 Raman spectroscope, SEM 측정 하였으며, TFT 제작 후, VG-ID, VD-ID 측정을 통해 전기적 특성인 Threshold voltage, Subthreshold swing, Field effect mobility, ON/OFF current ratio를 비교해 보았다.

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Poly (4-vinylphenol) 게이트 절연체를 적용한 IGZO TFT의 열처리 온도에 따른 전기적 특성 분석 (Electrical Characteristic Analysis of IGZO TFT with Poly (4-vinylphenol) Gate Insulator according to Annealing Temperature)

  • 박정현;정준교;김유정;정병준;이가원
    • 반도체디스플레이기술학회지
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    • 제16권1호
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    • pp.97-101
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    • 2017
  • In this paper, IGZO thin film transistor (TFT) was fabricated with cross-linked Poly (4-vinylphenol) (PVP) gate dielectric for flexible, transparent display applications. The PVP is one of the candidates for low-temperature gate insulators. MIM structure was fabricated to measure the leakage current and evaluate the insulator properties according to the annealing temperature. Low leakage current ( <0.1nA/cm2 @ 1MV/cm ) was observed at $200^{\circ}C$ annealing condition and decreases much more as the annealing temperature increases. The electrical characteristics of IGZO TFT such as subthreshold swing, mobility and ON/OFF current ratio were also improved, which shows that the performance of IGZO TFTs with PVP can be enhanced by reducing the amount of incomplete crosslinking in PVP.

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A New SOI LDMOSFET Structure with a Trench in the Drift Region for a PDP Scan Driver IC

  • Son, Won-So;Kim, Sang-Gi;Sohn, Young-Ho;Choi, Sie-Young
    • ETRI Journal
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    • 제26권1호
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    • pp.7-13
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    • 2004
  • To improve the characteristics of breakdown voltage and specific on-resistance, we propose a new structure for a LDMOSFET for a PDP scan driver IC based on silicon-on-insulator with a trench under the gate in the drift region. The trench reduces the electric field at the silicon surface under the gate edge in the drift region when the concentration of the drift region is high, and thereby increases the breakdown voltage and reduces the specific on-resistance. The breakdown voltage and the specific on-resistance of the fabricated device is 352 V and $18.8 m{\Omega}{\cdot}cm^2$ with a threshold voltage of 1.0 V. The breakdown voltage of the device in the on-state is over 200 V and the saturation current at $V_{gs}=5V$ and $V_{ds}$=20V is 16 mA with a gate width of $150{\mu}m$.

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Insulator룰 후속처리한 a-IGZO TFT의 전기적특성 분석

  • 나관영;노용한
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2009년도 추계학술대회 논문집
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    • pp.58-58
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    • 2009
  • gate로 ITO가 150nm의 두께로 coating된 Glass위에 절연막인 SiNx를 각각 $150^{\circ}C$$200^{\circ}C$로 RTA한 후 channel layer 로 IGZO를 sputtering 하였다. 그 후 전극으로 Al을 evaporation 하였고 이렇게 만든 소자의 I-V 특성과 Transfer 분석을 통해 mobility, Threshold voltage등의 변화를 관찰하여 Insulator의 열처리가 IGZO TFT의 특성에 어떠한 효과를 주는지 분석하였다.

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Electrical Properties of OTFTs and Inverters by using Ink-Jet Printing with Polyvinylphenol Insulator and TIPS-Pentacene Semiconductor

  • Kang, Rae-Wook;Xu, Yong-Xian;Song, Chung-Kun
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2008년도 International Meeting on Information Display
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    • pp.651-653
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    • 2008
  • In this paper, we report electrical properties of OTFTs by using ink-jet printing with polyvinylphenol (PVP) for gate insulator and bis(triisopropylsilylenthynyl) pentacene (TIPS pentacene) for semiconductor. OTFTs produced the excellent performance with the mobility of $1.27\;cm^2/V.s$ for top contact structure(TCS) and inverter consisting of two OTFTs exhibited the gain of 6.75.

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A Flexible Amorphous $Bi_5Nb_3O_{15}$ Film for the Gate Insulator of the Low-Voltage Operating Pentacene Thin-Film Transistor Fabricated at Room Temperature

  • Kim, Jin-Seong;Cho, Kyung-Hoon;Seong, Tae-Geun;Choi, Joo-Young;Nahm, Sahn
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2010년도 춘계학술회의 초록집
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    • pp.17-17
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    • 2010
  • The amorphous $Bi_5Nb_3O_{15}$ film grown at room temperature under an oxygen-plasma sputtering ambient (BNRT-$O_2$ film) has a hydrophobic surface with a surface energy of $35.6\;mJm^{-2}$, which is close to that of the orthorhombic pentacene ($38\;mJm^{-2}$, resulting in the formation of a good pentacene layer without the introduction of an additional polymer layer. This film was very flexible, maintaining a high capacitance of $145\;nFcm^{-2}$ during and after 10s bending cycles with a small curvature radius of 7.5 mm. This film was optically transparent. Furthermore, the flexible, pentacene-based, organic thin-film transistors (OTFTs) fabricated on the polyethersulphone substrate at room temperature using a BNRT-$O_2$ film as a gate insulator exhibited a promising device performance with a high field effect mobility of $0.5\;cm^2V^{-1}s^{-1}$, an on/off current modulation of $10^5$ and a small subthreshold slope of $0.2\;Vdecade^{-1}$ under a low operating voltage of -5 V. This device also maintained a high carrier mobility of $0.45\;cm^2V^{-1}s^{-1}$ during the bending with a small curvature radius of 9 mm. Therefore, the BNRT-$O_2$ film is considered a promising material for the gate insulator of the flexible, pentacene-based OTFT.

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Polyethersulfone(PES) 및 유리 기판위에 제작된 PVP 게이트 절연막의 전기적 특성 (Electrical Properties of PVP Gate Insulation Film on Polyethersulfone(PES) and Glass Substrates)

  • 신익섭;공수철;임현승;박형호;장호정
    • 마이크로전자및패키징학회지
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    • 제14권1호
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    • pp.27-31
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    • 2007
  • 휨성 유기박막트랜지스터(organic thin film transistor, OTFT)를 제작하기 위하여 게이트 절연막으로 PVP(poly-4-vinylphenol) 유기막을 이용하여 MIM (metal-insulator-metal) 구조의 캐패시터 소자를 제작하였다. 유기 절연층의 형성은 Al/PES (polyethersulfone) 기판과 ITO/Glass 기판 위에 PVP를 용질로, PGMEA(propylene glycol monomethyl ether acetate)를 용매로 사용하였다 또한 열경화성 수지인 poly(melamine-co-(ormaldehyde)를 사용하여 cross-linked PVP 절연막을 합성하여 스핀코팅법으로 소자를 형성하였다. 제작된 소자에 대해 절연막 두께와 기판 종류에 따른 전기적 특성을 조사한 결과 Al/PES 기판을 사용하였을때 누설전류는 1.3 nA로 ITO/glass 기판을 사용했을때의 27.5 nA보다 크게 개선되었다. 또한 제작된 모든 캐패시터 소자의 정전용량은 $1.0{\sim}1.2nF/cm^2$ 범위로 나타났으며 계산값과 매우 유사한 결과를 얻을 수 있었다.

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Atomic Layer Deposited ZrxAl1-xOy Film as High κ Gate Insulator for High Performance ZnSnO Thin Film Transistor

  • Li, Jun;Zhou, You-Hang;Zhong, De-Yao;Huang, Chuan-Xin;Huang, Jian;Zhang, Jian-Hua
    • Electronic Materials Letters
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    • 제14권6호
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    • pp.669-677
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    • 2018
  • In this work, the high ${\kappa}$ $Zr_xAl_{1-x}O_y$ films with a different Zr concentration have been deposited by atomic layer deposition, and the effect of Zr concentrations on the structure, chemical composition, surface morphology and dielectric properties of $Zr_xAl_{1-x}O_y$ films is analyzed by Atomic force microscopy, X-ray diffraction, X-ray photoelectron spectroscopy and capacitance-frequency measurement. The effect of Zr concentrations of $Zr_xAl_{1-x}O_y$ gate insulator on the electrical property and stability under negative bias illumination stress (NBIS) or temperature stress (TS) of ZnSnO (ZTO) TFTs is firstly investigated. Under NBIS and TS, the much better stability of ZTO TFTs with $Zr_xAl_{1-x}O_y$ film as a gate insulator is due to the suppression of oxygen vacancy in ZTO channel layer and the decreased trap states originating from the Zr atom permeation at the $ZTO/Zr_xAl_{1-x}O_y$ interface. It provides a new strategy to fabricate the low consumption and high stability ZTO TFTs for application.

게이트 산화막 가장자리에 Air-cavity를 가지는 새로운 구조의 다결정 실리콘 박막 트랜지스터 (A New Poly-Si TFT Employing Air-Cavities at the Edge of Gate Oxide)

  • 이민철;정상훈;송인혁;한민구
    • 대한전기학회논문지:전기물성ㆍ응용부문C
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    • 제50권8호
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    • pp.365-370
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    • 2001
  • We have proposed and fabricated a new poly-Si TFT employing air-cavities at the edges of gate oxide in order to reduce the vertical electric field induced near the drain due to low dielectric constant of air. Air-cavity has been successfully fabricated by employing the wet etching of gate oxide and APCVD (Atmospheric pressure chemical vapor deposition) oxide deposition. Our experimental results show that the leakage current of the proposed TFT is considerably reduced by the factor of 10 and threshold voltage shift under high gate bias is also reduced because the carrier injection into gate insulator over the drain depletion region is suppressed.

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Detection of Streptavidin-Biotin Complexes Using a Highly Sensitive AlGaN/GaN-Based Extended-Gate MISHEMT-Type Biosensor

  • Lee, Hee Ho;Bae, Myunghan;Choi, Byoung-Soo;Shin, Jang-Kyoo
    • 센서학회지
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    • 제25권5호
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    • pp.320-325
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    • 2016
  • In this paper, we propose an AlGaN/GaN-based extended-gate metal-insulator-semiconductor high electron mobility transistor (MISHEMT)-type biosensor for detecting streptavidin-biotin complexes. We measure the drain current of the fabricated sensor, which varies depending on the antibody-antigen reaction of streptavidin with biotin molecules. To confirm the immobilization of biotin polyethylene glycol (PEG) thiol, we analyze the Au surface of a GaN sample using X-ray photoelectron spectroscopy (XPS). The proposed biosensor shows higher sensitivity than Si-based extended-gate metal oxide semiconductor field effect transistor (MOSFET)-type biosensor. In addition, the proposed AlGaN/GaN-based extended-gate MISHEMT-type biosensor exhibits better long-term stability, compared to the conventional AlGaN/GaN-based MISHEMT-type biosensor.